Charged Device Model ESD Research Articles

Full-Component Modeling and Simulation of Charged Device Model ESD

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits.

Evaluating the CDM-Robustness of the input buffer with very fast transmission line pulse

In this paper, a scheme for how to utilize VFTLP (very fast transmission line pulse) data to design an input buffer circuit for CDM (charged-device model) ESD protection is reported. The impedance of the ESD device under VFTLP stress is nearly 120Ω at the beginning of turn-on transient, and decreases with time toward 10Ω prior to the voltage falling below 0V. In this work, the fact that the dynamic-characteristic impedance of the ESD device under VFTLP testing is independent of the stress current is found. Since both VFTLP zapping and the CDM are nanosecond events, the dynamic-characteristic impedance of the ESD device can be used to evaluate the CDM threshold voltage of the input buffer based on the equivalent and simplified RLC circuit.

(Invited) Reliability Aspects of Advanced IC Technology with ESD and Anti-Radiation Capabilities

Today's IC design squeezes millions of gates and 100s ofproven blocks into a single SoC chip, huge efforts have ever been put together into aftermath chip verifications, testing and debugging processes. Failure analysis such as ESD damages, and/or together with SEU (single event upset) by outer space radiations has also become rather impractical. Killer issues arising from intrinsic and extrinsic charge built ups can no longer be prevented by embedded ESD devices of I/O circuit itself. This work will first summaries the rising trend of ESD damages other than human body model (HBM) and machine model (MM) from external sources, also the intrinsic defects from the silicon materials and the associated malfunctions caused by design and backend integrations, then it intends to address a much overlooked 'design for reliability' in line with the DFM and DFY on 65nm technology and below with focus on the less reported CDM (charged device model) ESD damages. Capabilities of anti-radiation effect will be discussed in this work.

Analysis of charged device model (CDM) ESD in MEMS

The effect of charge injection due to CDM ESD in capacitive MEMS structures is analyzed. The results show that as feature size is reduced, ESD injected charge produces a change for the stiction effect which is inversely proportional to the square of the plate area and a change in the dielectric layer breakdown which is inversely proportional to the plate area. An electric field model is developed to examine charge and voltage modes in MEMS. A charge injection test method is proposed to determine the susceptibility of MEMS to CDM ESD.

On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100ns TLP system. From the HBM/CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1kV, MM 100V and CDM 500V.

The impact of ground plane size upon the performance of Field-induced Charged Device Model ESD testing systems

Experimental measurements of peak stressing current in a laboratory prototype Field-induced Charged Device Model (FCDM) ESD testing system have revealed a nonlinear dependence upon ground plane area and test module capacitance. This dependence is explained by an expanded equivalent circuit model for the testing system that takes explicit account of the parasitic capacitance between the ground plane on the test head and the underlying field plate. The results of this work underscore the importance of ensuring that the ground plane is sufficiently large to cover the device under test.

Characterization and modeling of transient device behavior under CDM ESD stress

Very-fast high-current pulses that occur during charged device model (CDM) ESD events lead to transient voltage overshoots in forward- and reverse-biased pn-junctions, called forward recovery and dynamic reverse overshoot. To improve the device modeling for CDM circuit simulation of integrated circuits, these effects should be fully understood and should be implemented in the device models. In this paper the effects are studied under the CDM relevant operating conditions by experimental characterization and device simulation. Technological parameters have been varied to assess the presence of the effects in different technologies, such as sub-micron CMOS technologies and smart power technologies. A simple compact model extension to include the forward recovery effect in diode models is presented. A novel parameter extraction method that uses the transient TDR signals of the very-fast TLP method is introduced. Using this extraction method we can parameterize high-current device models in the nanosecond time scale. The parameter extraction method is demonstrated by applying it to the modeling of the forward recovery effect.

Issues concerning charged device model ESD verification modules − the need to move to alumina

In this work, we demonstrate that both capacitance and inductance must be the central parameters associated with the charged device model (CDM) waveform verification modules. We also propose a change from the previously used FR-4 dielectric material substrate to a more stable alumina. This improves waveform repeatability and will lead to better correlation of test results. This paper completes the groundwork for a full ESDA CDM device testing standard.