Abstract
Today's IC design squeezes millions of gates and 100s ofproven blocks into a single SoC chip, huge efforts have ever been put together into aftermath chip verifications, testing and debugging processes. Failure analysis such as ESD damages, and/or together with SEU (single event upset) by outer space radiations has also become rather impractical. Killer issues arising from intrinsic and extrinsic charge built ups can no longer be prevented by embedded ESD devices of I/O circuit itself. This work will first summaries the rising trend of ESD damages other than human body model (HBM) and machine model (MM) from external sources, also the intrinsic defects from the silicon materials and the associated malfunctions caused by design and backend integrations, then it intends to address a much overlooked 'design for reliability' in line with the DFM and DFY on 65nm technology and below with focus on the less reported CDM (charged device model) ESD damages. Capabilities of anti-radiation effect will be discussed in this work.
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