Charge Trapping Memory Research Articles

Effect of oxygen vacancy on lattice and electronic properties of HfO2 by means of density function theory study

HfO2, as a gate dielectric material for the charge trapping memory, has been studied extensively due to its merits such as high k value, good thermal stability, and conduction band offset relative to Si, etc.. In order to understand the reason why the charge trapping efficiency is improved by high k capture layer with respect to charge trapping type memory, the variation of HfO2 crystal texture induced by oxygen vacancy and the influences of it are investigated using the first principle calculation based on density functional theory. Results show that the distance of the nearest neighbor oxygen atom from oxygen vacancy is markedly reduced after optimization, whereas the decrease of distances between the next nearest neighbor oxygen atom from oxygen vacancy and hafnium is less. The change of local crystal lattice is caused by optimized oxygen vacancy for it significantly changes the local lattice, but rarely influences the far lattice. Deep energy level and density of electron states in conduction band are contributed by Hf atoms, while the density of electron states in valence band is contributed by O atoms. The local density of electron states in each element and the total density of electron states in the optimization system are all larger than those in the system without optimization, and the sum of the local densities of electron states is less than the total density of electron states. The trapped charges are moving mainly around the oxygen vacancy and the adjacent atoms of oxygen in the optimization system, but the charges are without optimization throughout the system. The local energy of charge is increased in optimized defect system, while the local energy of charge is conspicuously reduced in the system without optimization, i.e. lattice variation without saturation characteristic has a large effect on the local energy of charge. Results further prove that the change of crystal lattice induced by oxygen vacancy has strong ability to capture charge, which helps improve the features of memory.

Tunable charge-trap memory based on few-layer MoS2.

Charge-trap memory with high-κ dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered two-dimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their fantastic physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Because of the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. Importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 10(4), allowing for multibit information storage. Moreover, the device shows a high endurance of hundreds of cycles and a stable retention of ∼ 28% charge loss after 10 years, which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-κ charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.

The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

The memory structures Pt/Al2O3/(TiO2)x(Al2O3)1−x/Al2O3/p-Si(nominal composition x = 0.05, 0.50 and 0.70) were fabricated by using rf-magnetron sputtering and atomic layer deposition techniques, in which the dielectric constant and the bottom of the conduction band of the high-k composite (TiO2)x(Al2O3)1−x were adjusted by controlling the partial composition of Al2O3. With the largest dielectric constant and the lowest deviation from the bottom of the conduction band of Si, (TiO2)0.7(Al2O3)0.3 memory devices show the largest memory window of 7.54 V, the fast programming/erasing speed and excellent endurance and retention characteristics, which were ascribed to the special structural design, proper combination of dielectric constant and band alignment in the high-k composite (TiO2)0.7(Al2O3)0.3.

Defect states and charge trapping characteristics of HfO2 films for high performance nonvolatile memory applications

In this work, we present significant charge trapping memory effects of the metal-hafnium oxide-SiO2-Si (MHOS) structure. The devices based on 800 °C annealed HfO2 film exhibit a large memory window of ∼5.1 V under ±10 V sweeping voltages and excellent charge retention properties with only small charge loss of ∼2.6% after more than 104 s retention. The outstanding memory characteristics are attributed to the high density of deep defect states in HfO2 films. We investigated the defect states in the HfO2 films by photoluminescence and photoluminescence excitation measurements and found that the defect states distributed in deep energy levels ranging from 1.1 eV to 2.9 eV below the conduction band. Our work provides further insights for the charge trapping mechanisms of the HfO2 based MHOS devices.

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

Charge Trap Flash (CTF) memory devices, otherwise known as metal-oxide-nitride-oxide-silicon structures, have been the subject of attention in the semiconductor industry due to their advantages over conventional floating gate type memory. These advantages include lower programming voltage, superior programming/erasing speeds, and a simple fabrication process compatible with standard complementary metal-oxidesemiconductor technology [1-3]. Recently, CTF memory devices have gained increasing interest in the three dimensional (3D) integration for next generation nonvolatile memory technology [4,5]. The tunnel oxide thickness plays a crucial role in regulating the erasing speed, data retention characteristics and charge loss mechanisms for CTF memory devices [6], while the thickness of the nitride charge trapping layer is less critical. Nevertheless, in 3D architectures, the nitride thickness has a direct effect on charge storage performance and array density [7]. Moreover, temperatures [8] and trap energy levels [9,10] also are considerable factors for understanding the electron loss mechanisms. Hence, in this letter, Pt/Al2O3/Si3N4/SiO2/Si (MANOS) charge trapping memory capacitors with various thicknesses of nitride layer were fabricated. We investigated and analyzed the effect of nitride thickness, trap energy levels and temperatures on electrons loss behavior in the retention state for MANOS capacitors. Also, a reasonable nitride thickness range was obtained through electrical characteristic measurements. Four charge loss mechanisms [11,12] are involved in the data retention state for scaled CTF memory devices: trapped electrons tunnel from traps to the silicon conduction band (T-B), trapped electrons Zhenjie Tang, Ma Dongwei, Zhang Jing, Jiang Yunhong, and Wang Guixia College of Physics and Electronic Engineering, Anyang Normal University, Anyang 455000, P.R.China

High-performance transparent, all-oxide nonvolatile charge trap memory transistor using In-Ga-Zn-O channel and ZnO trap layer

A transparent, nonvolatile all-oxide charge-trap memory transistor (Ox-CTMT) was fabricated with a bottom-gate structure on a glass substrate. A wide memory window of 7.7 V was achieved when the amplitude and duration of program voltage pulses were set as ±20 V and 100 ms, respectively. The values of saturation mobility and subthreshold swing were 0.43 cm2 V−1 s−1 and 0.46 V/dec, respectively. Thanks to the unique band structure of the n-type ZnO oxide semiconductor, the fabricated Ox-CTMT exhibited a memory margin of more than four orders of magnitude for on and off states even after a lapse of 10 000 s.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement.

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future.

Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories

This study experimentally examines the reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories. Unique Schottky barrier junctions strongly enhance hot-carrier generation, ensuring high-speed multi-level programming at low gate voltages. However, strong injected gate currents might cause potential retention and endurance concerns when the programming voltage is beyond 9V. The effective number of deep-level traps is insufficient for capturing injected electrons, such that some electrons occupy shallower states, producing retention degradation after thermal stress. The charge-trapping layers are susceptible to additional trap generation under strong gate currents, leading to considerable threshold-voltage shifts after cycling stress. A compromise of cell characteristics exists between excellent reliability and high-speed programming in 3-bit/cell Schottky barrier nanowire cells. The application of sub-8-V multi-level programming can alleviate the potential reliability generated by strong injected currents, preserving a favorable cycling endurance and thermal retention in 3-bit/cell Schottky barrier nanowire charge-trapping cells.

The dominant factors affecting the memory characteristics of (Ta2O5)x(Al2O3)1−x high-k charge-trapping devices

The prototypical charge-trapping memory devices with the structure p-Si/Al2O3/(Ta2O5)x(Al2O3)1−x/Al2O3/Pt(x = 0.5, 0.3, and 0.1) were fabricated by using atomic layer deposition and RF magnetron sputtering techniques. A memory window of 7.39 V with a charge storage density of 1.97 × 1013 cm−2 at a gate voltage of ±11 V was obtained for the memory device with the composite charge trapping layer (Ta2O5)0.5(Al2O3)0.5. All memory devices show fast program/erase speed and excellent endurance and retention properties, although some differences in their memory performance exist, which was ascribed to the relative individual band alignments of the composite (Ta2O5)x(Al2O3)1−x with Si.

Coupling of carriers injection and charges distribution in Schottky barrier charge-trapping memories using source-side electrons programming

This study elucidates the coupling of Schottky barriers and trapped charges involved in the source-side electrons programming and two-bit/cell reading of the Schottky barrier charge-trapping cells. Two-dimensional numerical iterations were employed to examine the distribution of electron injections and trapped charges, and to discuss the differences of physical mechanisms between the Schottky barrier and conventional cells. In the Schottky barrier cells, both the conduction and injection of electron carriers depend on the Schottky source barrier lowering. The source-side trapped charges alter the source-side lateral field distribution, reducing the maximum of the lateral electric field, and moving the subsequent injections away from the source edge. The distribution of total trapped-charges is considerably wider than that of the initial injection. However, because of source-side conduction, the excellent screening of second-bit effect is beneficial to operate the NOR-type multibit/cell charge-trapping memories.

Low Power Zinc-Oxide Based Charge Trapping Memory with Embedded Silicon Nanoparticles

In this work, a bottom-gate charge trapping memory device with Zinc-Oxide (ZnO) channel and 2-nm Si nanoparticles (Si-NPs) embedded in ZnO charge trapping layer is demonstrated. The active layers of the memory device are deposited by atomic layer deposition (ALD) and the Si-NPs are deposited by spin coating. The Si-NPs memory exhibits a threshold voltage (Vt) shift of 6.3 V at an operating voltage of -10/10 V while 2.6 V Vt shift is obtained without nanoparticles confirming that the Si-NPs act as energy states within the bandgap of the ZnO layer. In addition, a 3.4 V Vt is achieved at a very low operating voltage of -1 V/1 V due to the charging of the Si-NPs through Poole-Frenkel emission mechanism at an electric field across the tunnel oxide E > 0.36 MV/cm. The results highlight a promising technology for future ultra-low power memory devices.

A review of nanographene: growth and applications

Graphene's unique physical and chemical properties have attracted substantial interest for various potential applications for electronics, spintronics, optoelectronics, and so on. Nanographene not only has the properties of graphene, but also has the special properties of edge state. Direct growth of nanographene on arbitrary substrate without catalyst has advantage of simplicity in device fabrications. In this paper, we review our recent progress on direct growth of nanographene on various substrates and using these nanographene as building blocks for electronic devices. The growth process is catalyst-free, scalable, and of low-temperature. Strain sensor, charge trapping memory (CTM) and resistance random access memory (RRAM) with excellent performances are demonstrated by tuning the size and density of as-grown nanographene on substrates.

Drain-induced Schottky barrier source-side hot carriers and its application to program local bits of nanowire charge-trapping memories

A new mechanism of drain-induced Schottky barrier lowering is reported experimentally for Schottky barrier nanowire devices. The strong drain-induced barrier lowering and associated source-side hot electrons were employed to program the localized bits of nanowire charge-trapping memory cells. For Schottky barrier nanowire devices, two different mechanisms of Schottky barrier lowering are classified: 1) gate-controlled and 2) drain-induced. In the drain-mode conduction, the lowering of Schottky source barrier relies on the drain voltage. The smaller gate voltage and the larger drain voltage are, the higher drain current is attained. The pure drain-induced current can locally program the nanowire charge-trapping cells at a drain voltage of 5–6 V. The decoupled forward and reverse reading curves confirm the trap charges are sorely programmed at the source-side region. This new drain-induced lowering mechanism provides a practical approach to program the multi-bit/cell NOR-type nanowire charge-trapping memories, and the drain-mode programming preserves excellent thermal retention and cycling endurance.

Transparent Graphene Nanoplatelets for Charge Storage in Memory Devices

Recently, graphene has been considered as a promising material for future low cost electronics because of its noteworthy properties, such as high carrier mobility, large work-function, thermal conductivity, structural robustness and optical transparency [1]. In this work, transparent graphene nanoplatelets are investigated for charge storage layers in low-cost non-volatile charge trapping memory devices. The memory electrical characterization, retention and endurance characteristics, and charge emission mechanism are analyzed. The memory cells are fabricated on an n+-type (111) (Antimony doped, 15-20 mµÙ-cm) Si wafer. 10-nm-thick Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system. Pristine graphene nanoplatelets (NanoIntegris PureSheets Quattro grade) are deposited by drop-casting technique. Samples are placed on hot-plate at 110°C and 2-2.5 ml of 0.05 mg/ml graphene solution is drop-casted slowly by using plastic pipette and samples are left to dry for 5 minutes on hot-plate. Then a 5-nm-thick Al2O3 tunnel oxide is ALD deposited at 250°C. A 400-nm-thick Al layer for the gate contact is sputtered using a shadow mask. A cross-sectional illustration of the fabricated memory device is depicted in Fig. 1a).Then, the memory devices are electrically characterized by measuring the C-Vgate characteristics of the programmed and erased states at high frequency (1 MHz). Using the Agilent B1505A Semiconductor Device Parameter Analyzer, the memory cells gate voltage was first swept from -10 V forward to 10 V. The obtained C-V characteristic corresponds to the erased state as shown in Fig. 1b). Then, upon sweeping the gate voltage from +10 V to -10 V, there was a near parallel shift in the measured C-V curve in the positive direction as seen in Fig. 1b). The positive shift is due to electrons storage in the graphene nanoplatelets and the value of the Vt shift is 4.4 V. The Vt is extracted at a capacitance of 500 pF at the onset of the depletion region. The measured memory window at different operating voltages indicates a large Vt shift (3.6 V) at low operating voltages (8/-8 V). At 10/-10 V, the charge trap states density of the graphene is calculated and found to be 5.83×1012 cm-2 [2]. Furthermore, to identify the electron emission mechanism, the electric field across the tunnel oxide is calculated [3] and the natural logarithm of the Vt shift divided by the square of the electric field is plotted vs. the reciprocal of the electric field as shown in Fig. 2. In Fowler-Nordheim tunneling (F-N), the charges are injected by tunneling into the conduction band of the oxide through a triangular energy barrier and then are swept by the electric field into the charge trapping layer. The emission rate of charges in F-N tunneling is exponentially proportional to the reciprocal of the electric field times the electric field squared [3]. Thus, the linear trend presented in Fig. 2 indicates that the dominating electron emission mechanism at electric fields larger than 5.6MV/cm (corresponding to a gate voltage of 6V) is F-N tunneling. Finally, the fabrication of such graphene based memory structure is compatible with existing semiconductor processing thus has potential on low-cost integrated nanoscale memory applications. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815. References N. El-Atab, A. Ozcan, S. Alkis, A. K. Okyay, and A. Nayfeh "Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission", Appl. Phys. Lett. 104, 013112 (2014).F. Schwierz, Graphene transistors. Nat. Nanotechnol. 5, 487–496 (2010).S. M. SZE, “Nonvolatile Memory Devices,” in Physics of Semiconductor Devices, 3rd ed. New Jersey: Wiley, 2007.

The Study of Charge Trapping in Mahas Memory Structure with Various HfO2 Trap Layer Thicknesses

Recently, charge trap type memory devices are developed to replace the conventional floating-gate flash memories for high quality memory operation in dense memory cell array. However, memory reliability characteristic degradations have arisen from the tunnel oxide thickness scale down in the ‘ONO’ (SiO2/Si3N4/SiO2) type charge trap memory. To overcome this limitation, high-k dielectrics have been attempted by replacing the charge trap layer (CTL) SiNx / blocking layer (BL) SiO2. Especially, HfO2 and Al2O3 have been mainly developing for CTL and BL, respectively. But, it is still required to investigate the high-k dielectrics scale down for improvement of memory performance. In this study, optimized thickness of the HfO2 CTL was investigated in Junctionless devices with poly silicon channel. Increase Step Pulse Program (ISPP) characteristic in HfO2 CTL device show less sensitive to thickness scale down than SiNx CTL device. But, under the 6nm of HfO2 thickness, ISPP slope degradation was observed by high applied voltage pulse. It is expected that amount of tunneling electron through the Al2O3 BL is increased by decrement of dielectric thickness. By program/erase results, 4.6nm SiNx CTL device show poor erase characteristic comparison with HfO2 CTL device. Consequently, very slow program and erase operation during endurance test was observed in SiNx CTL device. For these results, we are expected that optimized HfO2 CTL can be replaced conventional SiNx CTL for next generation NAND flash memory.

Enhanced memory effect with embedded graphene nanoplatelets in ZnO charge trapping layer

A charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO (GNIZ) is demonstrated. The memory shows a large threshold voltage Vt shift (4 V) at low operating voltage (6/−6 V), good retention (>10 yr), and good endurance characteristic (>104 cycles). This memory performance is compared to control devices with graphene nanoplatelets (or ZnO) and a thicker tunnel oxide. These structures showed a reduced Vt shift and retention characteristic. The GNIZ structure allows for scaling down the tunnel oxide thickness along with improving the memory window and retention of data. The larger Vt shift indicates that the ZnO adds available trap states and enhances the emission and retention of charges. The charge emission mechanism in the memory structures with graphene nanoplatelets at an electric field E ≥ 5.57 MV/cm is found to be based on Fowler-Nordheim tunneling. The fabrication of this memory device is compatible with current semiconductor processing, therefore, has great potential in low-cost nano-memory applications.

Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm.

Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly.

Enhanced charge storage performance in AlTi4Ox/Al2O3 multilayer charge trapping memory devices

The charge-trapping memory devices with the structures p-Si/Al2O3/AlTi4Ox/Al2O3/Pt were fabricated by using atomic layer deposition and RF magnetron sputtering techniques, and a memory window of 6.61 V and a high charge-trapping density of 1.29 × 1013 cm−2 at gate voltage of ±11 V have been obtained. The remarkable charge-trapping effect in the high-k composite oxide layer was ascribed to the electron-occupied defect states formed by the inter-diffusion at the interface of TiO2/Al2O3. An Al2O3 layer intercalated in the charge-trapping layer AlTi4Ox enlarged the memory window to 14.59 V and also improved the data retention property by suppressing the vertical charge migration.

Growth of high-density Ir nanocrystals by atomic layer deposition for nonvolatile nanocrystal memory applications

A careful investigation is made of the growth of Ir nanocrystals (NCs) on Al2O3 by atomic layer deposition (ALD), and a charge trapping memory device using ALD-grown Ir NCs as the charge trapping layer and ALD-grown Al2O3/HfO2 as the tunneling/blocking layers is fabricated. It is found that the ex situ nucleation of Ir NCs on ALD-grown Al2O3 is difficult, though in situ growth can produce pure metallic Ir NCs with a face-centered cubic crystalline phase directly on ALD-grown Al2O3 at the initial growth stage, which follows the nucleation incubation model. The growth of these metallic Ir NCs is attributed to the presence of a uniform coverage of reactive groups (hydroxyl or dimethylaluminum) on the as-deposited fresh ALD-grown Al2O3 surface, which greatly promotes the uniform nucleation of Ir. Electrical measurements of p-Si/Al2O3/Ir NCs/HfO2 memory cells exhibit a large memory window of 4.2 V at the sweeping gate voltage of ±10 V, and a ∼76% retention property after 104 s at 75 °C. Also, a stable memory window of ∼2 V is achieved during the first 105 program/erase cycles under a ±10 V/10 ms program/erase operation. In situ ALD-grown Ir NCs with the highest density of 0.6 × 1012/cm2 provide a potential approach to fabricate large-area high-density NCs for future ultrahigh-density nonvolatile NC memory applications.

Enhanced memory effect via quantum confinement in 16 nm InN nanoparticles embedded in ZnO charge trapping layer

In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al2O3 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-Vgate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4 V, the memory shows a noticeable threshold voltage (Vt) shift of 2 V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5 V is achieved and the Vt shift direction indicates that electrons tunnel from channel to charge storage layer.