Charge Trapping Memory Research Articles

Improvement of charge trapping memory performance by modulating band alignment with oxygen plasma

Metal-oxide charge trapping memory (CTM) integration into amorphous and organic flexible devices encounters challenges due to high-temperature treatment. Our approach enhances memory performance via room-temperature oxygen plasma treatment, subtly adjusting surface band alignment without changing the original material structure and surface roughness. Infiltration of oxygen plasma induces band alignment bending, creating a barrier for charge trapping. The device with oxygen plasma treatment exhibits an impressive 19.06 V memory window and a charge trapping density of 3.58 × 1013/cm2. In comparison, the memory window of untreated device only has 5.56 V, demonstrating that oxygen plasma treatment significantly improves memory characteristics. The charge retention rate exhibits outstanding stability, potentially reaching 94% after a decade. It should be noted that careful control during plasma treatment is crucial to maintaining optimal memory effects. This facile, efficient technique, applicable to various oxide layers, offers a way for future advancements in metal-oxide CTM technology.

Enhancing Charge Trapping Performance of Hafnia Thin Films Using Sequential Plasma Atomic Layer Deposition.

We aimed to fabricate reliable memory devices using HfO2, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (Dit) reached a minimum value of 1.0 × 1012 eV-1cm-2. Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO2/HfO2 interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput.

Advanced spectroscopic methods for probing in-gap defect states in amorphous SiNx for charge trap memory applications

Silicon nitride (SiNx) serves as the charge trap layer in current 3D NAND flash memory devices. The precise formation mechanism and electronic structure of localized defect trap states in SiNx remain elusive. Here, we present a refined experimental methodology to elucidate the in-gap defect states and the band gaps in amorphous SiNx thin films. Our approach integrates high-resolution reflection electron energy loss spectroscopy (REELS) and spectroscopic ellipsometry (SE) for comprehensive analysis. By systematical analysis, we aim to provide a robust method for determining in-gap electronic states in SiNx. We investigated two different SiNx films prepared by plasma-enhanced chemical vapor deposition and sputtering. Our analysis revealed several distinct in-gap states and determined band gap energies. This approach not only provide advanced spectroscopic methods to characterize the defect electronic states in SiNx, but also applicable to other large band gap semiconductors or dielectrics to predict device-level characteristics for future devices.

Recent Progress in Memrsitor Array Structures and Solutions for Sneak Path Current Reduction

AbstractMemristors have diverse potential for improving data storage through linear memory control and synaptic operation in AI and neuromorphic computing. Prior research on optimizing memristors in next‐generation devices has generally indicated that emerging arrays and vertical structures can improve memory density, although special fabrication steps are required to realize improved operation. Until now, many obstructions, such as the sneak path current and forming processes from the initial device in array structure operation at the device level, have limited the development of array‐based memristor devices for further progressing circuits and integrated design. In this paper, memristor array studies are examined that have suggested solutions for sneak path current and forming operation problems at the device level. Ultimately, representative solutions are proposed to progress memristors into array structures by introducing the latest research on one diode‐one RRAM (1D1R), one selector‐one RRAM (1S1R), overshoot suppressed RRAM (OSRRAM), self‐rectifying cell (SRC), charge trap memory (CTM) and their applications. Additionally, essential details demonstrating the practical implementation of these devices in crossbar array memory are investigated. Finally, the advantages and perspectives of these array‐based memristor solutions are summarized.

GaN-Based Charge Trapping Memory With an AlN Interfacial Layer for Multi-State Operation

GaN-Based Charge Trapping Memory With an AlN Interfacial Layer for Multi-State Operation

Impact of channel thickness on device scaling in vertical InGaZnO channel charge-trap memory transistors with ALD Al2O3 tunneling layer

This study investigates the impact of channel thickness (TCH) variation on memory performance and its physical origins in vertical channel charge trap memory (V-CTM) using InGaZnO (IGZO) channels for X–Y scaling. When the TCH decreased, the subthreshold slope (SS) increased from 0.21 to 0.30 V/dec, while the minimum program voltage decreased from 12 to 8 V, indicating a performance trade-off. The analysis of bulk trap density extracted by SS, density of states distribution, and x-ray photoelectron spectroscopy confirmed an increase in the number of trap states and hydrogen-related defects in the IGZO channel when a thin TCH is employed. As a result, it was expected that the barrier height at the active layer/TL would be lowered during program operations at relatively thin channel. However, the SS would also be degraded due to an increase in sub-gap states, such as OH- and VOH, induced by hydrogen incorporation. The V-CTM with an optimal TCH of 7 nm had a maximum memory window of 5.7 V. The program/erase states were maintained for 106 s before experiencing a 50 % charge loss, and 5-level memory states were verified to be available within a memory window of 3.2 V for 108 s with little degradation. It was noteworthy that the long-term reliability and multilevel implementation could be secured for the V-CTM with a TCH as thin as 7 nm, demonstrating the sound feasibility of its X–Y scaling. This work presents new key parameters and understanding of device integration issues for future 3D structured memory transistors, and aims to contribute to the advancement of memory technologies using oxide semiconductor channels.

Atomic Layer Deposited Ta2O5-x Nano-Islands for Charge Trapping Memory Devices

The charge trapping memory (CTM) boasts numerous advantages to replace conventional flash memory. In this work, atomic layer deposited Ta2O5-x nano-islands were employed as charge trapping units in Pt/Al2O3/Ta2O5-x nano-islands/Al2O3/Si...

Random Telegraph Noise and Radiation Response of 80 nm Vertical Charge-Trapping NAND Flash Memory Devices with SiON Tunneling Oxide

Random Telegraph Noise and Radiation Response of 80 nm Vertical Charge-Trapping NAND Flash Memory Devices with SiON Tunneling Oxide

A carbonyl-decorated two-dimensional polymer as a charge-trapping layer for non-volatile memory storage devices with a high endurance and wide memory window.

The charge-trapping mechanism in conjugated polymers is a performance obstacle in many optoelectronic devices harnessed for non-volatile memory applications. Herein, a carbonyl-decorated organic 2D-polymer (TpDb)-based charge-trapping memory device has been developed with a wide memory window (3.2 V) with low programming and erasing voltages of +3/-2 and -3/+2. The TpDb was synthesized by a potentially scalable solid-state aldol condensation reaction. The inherent structural defects and the semi-conjugated nature of the enone network in TpDb offer effective charge-trapping through the localization of charges in specific functional groups (CO). The interlayer hydrogen bonding enhances the packing density of the 2D-polymer layers thereby improving the memory storage properties of the material. Furthermore, the TpDb exhibits excellent features for non-volatile memory applications including over 10 000 cycles of write/read endurance and a prolonged retention performance of 104 seconds at high temperatures (100 °C).

Total ionizing dose response of 128 analog states in computational charge-trap memory

Total ionizing dose response of 128 analog states in computational charge-trap memory

Enhanced charge trapping characteristics through composite high-k material phase separation

Charge trapping memory with the P-Si/Al2O3/LaTiO/Al2O3/Pt structure was fabricated by a pulsed laser deposition system. An innovative high-k nanocrystal-amorphous phase structure could be stably formed in the charge trapping layer. The La2O3 nanocrystals are embedded in amorphous TiO2. Numerous charge traps are generated at the phase interface, which could significantly increase the charge trapping capability. A larger memory window of 16.56 V at ±12 V sweep voltage is observed, comparing with a lower value of 5.52 V for the simple amorphous structure. The device also demonstrated excellent stability, with only a 13% charge loss rate after 10 years and an unchanged memory window after 105 program/erase cycles. It is attributed to the structure that the amorphous phase isolates the trapped electrons around the nanocrystal and, thus, is resistant to loss. This work could provide an approach to generating charge traps by phase separation of high-k materials for future nonvolatile memory applications.

Nano-scale charge trapping memory based on two-dimensional conjugated microporous polymer

There is a growing interest in new semiconductor nanostructures for future high-density high-performance flexible electronic devices. Two-dimensional conjugated microporous polymers (2D-CMPs) are promising candidates because of their inherent optoelectronic properties. Here, we are reporting a novel donor–acceptor type 2D-CMP based on Pyrene and Isoindigo (PI) for a potential nano-scale charge-trapping memory application. We exfoliated the PI polymer into ~ 2.5 nm thick nanoparticles (NPs) and fabricated a Metal–Insulator–Semiconductor (MIS) device with PI–NPs embedded in the insulator. Conductive AFM (cAFM) is used to examine the confinement mechanism as well as the local charge injection process, where ultrathin high-κ alumina supplied the energy barrier for confining the charge carrier transport. We have achieved a reproducible on-and-off state and a wide memory window (ΔV) of 1.5 V at a relatively small reading current. The device displays a low operation voltage (V < 1 V), with good retention (104 s), and endurance (103 cycles). Furthermore, a theoretical analysis is developed to affirm the measured charge carriers’ transport and entrapment mechanisms through and within the fabricated MIS structures. The PI–NPs act as a nanoscale floating gate in the MIS-based memory with deep trapping sites for the charged carriers. Moreover, our results demonstrate that the synthesized 2D-CMP can be promising for future low-power high-density memory applications.

Endurance Improvement of GaN Bipolar Charge Trapping Memory With Back Gate Injection

Endurance Improvement of GaN Bipolar Charge Trapping Memory With Back Gate Injection

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks.

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

Band gap energy and near infrared to ultraviolet complex optical properties of single crystal TbScO3

TbScO3 is a wide bandgap semiconductor with potential applications in charge trap memory devices and acts as an alternate gate dielectric in fully depleted transistors and also a substrate for epitaxial thin film growth. TbScO3 has an orthorhombic crystal structure, which gives rise to optical anisotropy. Generalized ellipsometric spectra are measured for multiple in-plane rotations of (110) and (001) oriented TbScO3 single crystals over a photon energy range of 0.7–8.5 eV to determine the complex dielectric function (ε = ε1 + iε2) spectra for electric fields oscillating along each axis. A direct bandgap is identified at 6.50 eV, and above gap critical point transitions are found at 6.99, 7.14, 7.16, 7.21, and 7.42 eV.

Amorphous GaOx based charge trap memory device for neuromorphic applications

In this work, we demonstrate a 3-terminal field-effect based charge trap memory device with an amorphous-GaOx (a-GaOx) layer fabricated at a low deposition temperature of 250°C. Utilizing the long life-time traps in the a-GaOx/Al2O3 stack, we study the charge trap memory effect in the field effect devices. We observe more than one order of magnitude in channel current difference for two memory states with a retention of more than 102 s and endurance of 100 cycles. Our work paves a way for embedded a-GaOx memories for neuromorphic applications.

Support Vector Regression Model for Determining Optimal Parameters of HfAlO-Based Charge Trapping Memory Devices

The production and optimization of HfAlO-based charge trapping memory devices is central to our research. Current optimization methods, based largely on experimental experience, are tedious and time-consuming. We examine various fabrication parameters and use the resulting memory window data to train machine learning algorithms. An optimized Support Vector Regression model, processed using the Swarm algorithm, is applied for data prediction and process optimization. Our model achieves a MSE of 0.47, an R2 of 0.98856, and a recognition accuracy of 90.3% under cross-validation. The findings underscore the effectiveness of machine learning algorithms in non-volatile memory fabrication process optimization, enabling efficient parameter selection or outcome prediction.

Charge-trap memory effect in spray deposited ZnO-based electrolyte-gated transistors operating at low voltage

Charge-trap memory phenomena were demonstrated in an electrolyte-gated transistor (EGT) using a spray-coated zinc oxide (ZnO) active layer and a cellulose-based electrolyte. The EGT exhibited efficient programming and erasing characteristics at low voltages, shifting the threshold voltage and the magnitude of the on-current. This behavior is discussed in terms of the influence of charged trapping states at the ZnO/electrolyte interface and within the ZnO bulk. The presence of these traps leads to a shift in the mobility from 0.57 ± 0.16 cm2 V−1 s−1 in the initial state to 0.02 ± 0.01 cm2 V−1 s−1 when programmed. Retention experiments revealed improved stability of the memory state when a low positive voltage is applied to the gate, indicating that the device's characteristics are extremely sensitive to the trapping/detrapping of charges at the semiconductor/electrolyte interface. Capacitance spectroscopy measurements using planar and metal-insulator-semiconductor configurations within the same device were used to analyze the charging dynamics of the trap states at different programming states.

Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices.

Optimization of equipment structure and process conditions is essential to obtain thin films with the required properties, such as film thickness, trapped charge density, leakage current, and memory characteristics, that ensure reliability of the corresponding device. In this study, we fabricated metal-insulator-semiconductor (MIS) structure capacitors using HfO2 thin films separately deposited by remote plasma (RP) atomic layer deposition (ALD) and direct-plasma (DP) ALD and determined the optimal process temperature by measuring the leakage current and breakdown strength as functions of process temperature. Additionally, we analyzed the effects of the plasma application method on the charge trapping properties of HfO2 thin films and properties of the interface between Si and HfO2. Subsequently, we synthesized charge-trapping memory (CTM) devices utilizing the deposited thin films as charge-trapping layers (CTLs) and evaluated their memory properties. The results indicated excellent memory window characteristics of the RP-HfO2 MIS capacitors compared to those of the DP-HfO2 MIS capacitors. Moreover, the memory characteristics of the RP-HfO2 CTM devices were outstanding as compared to those of the DP-HfO2 CTM devices. In conclusion, the methodology proposed herein can be useful for future implementations of multiple levels of charge-storage nonvolatile memories or synaptic devices that require many states.

Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors

ABSTRACT The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the p-type organic-based CTM shows the widest threshold voltage shift (∆VTH ≈ 80 V), four distinct V THs for a multi-bit memory operation and retained memory currents for 103 s with high memory on- and off-current ratio (IM,ON/IM,OFF ≈ 5Ⅹ104). The n-type oxide-based CTM (Ox-CTM) also shows a ∆V TH of 14 V and retained memory currents for 103 s with I M,ON/I M,OFF ≈ 104. The inability of the Ox-CTM to be electrically erasable is well explained with simulated electrical potential contour maps. It is deduced that, irrespective of the varied solution-processed semiconductor used, the RT-dried organic ZAA as CTL shows the best memory functionality in the fabricated CTMs. This implies that the high carbon double bonds in the low-temperature processed ZAA CTL are very useful for low-cost multi-bit CTMs in flexible electronics.