Charge Trapping Layer Research Articles

A Ferroelectric and Charge Hybrid Nonvolatile Memory—Part II: Experimental Validation and Analysis

Part I of this article introduced the concept and operation of the novel hybrid memory, integrating ferroelectric polarization and nonvolatile charge injection. In Part II, we demonstrate the experimental validation of this hybrid design. One-transistor memory cells were fabricated with polyvinylidene fluoride-trifluoroethylene [P(VDF-TrFE)] as the ferroelectric and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as the charge trap layer. Hybrid devices showed larger memory window and longer retention time compared to conventional FE-FETs with the same effective oxide thickness. Pulsed measurements were performed on metal-ferroelectric-metal capacitors to estimate switching delay in the P(VDF-TrFE) thin film. Field enhancement in the tunnel oxide resulted in pronounced electron injection from the gate compared with gate injection Flash memory cells. Hybrid devices also exhibited higher program efficiencies against the FE-FET due to the contribution from these injected electrons. The presence of the tunnel oxide in hybrid devices showed over 20× reduction in gate leakage, which resulted in 100 × improvement in cycling endurance against FE-FETs.

Memory Effect of Low-Temperature Processed ZnO Thin-Film Transistors Having Metallic Nanoparticles as Charge Trapping Elements

In this study, non-volatile memory effect was characterized using the single-transistor-based memory devices based on self-assembled gold nanoparticles (AuNP) as the charge trapping elements and atomic-layer deposited ZnO as the channel layer. The fabricated memory devices showed controllable and reliable threshold voltage shifts according to the program/erase operations that resulted from the charging/discharging of charge carriers in the charge trapping elements. Reliable non-volatile memory properties were also confirmed by the endurance and data retention measurements. The low temperature processes of the key device elements, i.e., AuNP charge trapping layer and ZnO channel layer, enable the use of this device structure to the transparent/flexible non-volatile memory applications in the near future.

Nonvolatile Poly-Si TFT Charge-Trap Flash Memory With Engineered Tunnel Barrier

Tunnel-barrier-engineered thin-film transistor (TFT) memory (TBE-TFT memory) devices on glass substrates were fabricated using low-temperature processes. An amorphous silicon film on the glass substrate was crystallized using excimer laser annealing for system-on-panel applications. The engineered tunnel barrier of VARIOT type (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> charge-trapping layer and an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> blocking layer was applied to TBE-TFT memory devices in order to enhance the memory performance of TBE-TFT memory devices. As a result, the poly-Si TFT charge-trap Flash memory with an engineered tunnel barrier exhibited excellent memory characteristics, such as large memory window (9.5 V), long retention time, and endurance.

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

The relationship between chemical structure (N/Si ratio) or physical structure (bilayer or laminate structure) of Si-rich nitride charge-trapping layer for metal–oxide–nitride–oxide–semiconductor (MONOS) type NAND flash memory and its electrical characteristics (including program/erase Vth window, fresh cell data retention and data retention after program/erase cycling stress) are investigated in detail. A bilayer charge-trapping structure formed by two different composite Si-rich nitride films has been developed that can realize a sufficient program/erase window and excellent data retention characteristics for multi-level cell (MLC) operation.

Additive-Driven Assembly of Block Copolymer–Nanoparticle Hybrid Materials for Solution Processable Floating Gate Memory

Floating gate memory devices were fabricated using well-ordered gold nanoparticle/block copolymer hybrid films as the charge trapping layers, SiO(2) as the dielectric layer, and poly(3-hexylthiophene) as the semiconductor layer. The charge trapping layer was prepared via self-assembly. The addition of Au nanoparticles that selectively hydrogen bond with pyridine in a poly(styrene-b-2-vinyl pyridine) block copolymer yields well-ordered hybrid materials at Au nanoparticle loadings up to 40 wt %. The characteristics of the memory window were tuned by simple control of the Au nanoparticle concentration. This approach enables the fabrication of well-ordered charge storage layers by solution processing, which is extendable for the fabrications of large area and high density devices via roll-to-roll processing.

Environment and baking influence on charge retention on silicon nitride charge trap layers

We report the charge storage capacity of silicon nitride using Kelvin force microscopy (KFM). KFM is performed under various environments and for different thicknesses of Si3N4 (3 nm, 6 nm, and 9 nm) on top of a 10-nm SiO2 blocking oxide. We prove increased storage capacity with increased thickness and strong localization of charge characteristics — under reduced surface contamination. We have found that surface contamination is here linked with baking and presence of nitrogen flux. The structure shows strong retention under ultra high vacuum and Si3N4 thickness dependency. The total charge stored in each of these structures is calculated using Poisson solver.

HfO2 nanoparticles embedded within a SOG-based oxide matrix as charge trapping layer for SOHOS-type memory applications

In this work, HfO2 nanoparticles (np-HfO2) are embedded within an amorphous Spin-On Glass (SOG)-based oxide matrix and used as charge-trapping layer for memory applications. Following specific thermal treatments, the np-HfO2 act as charge storage nodes able to retain charge injected after applying a constant gate voltage. A Silicon-Oxide-High-k-Oxide-Silicon (SOHOS)-type memory has been fabricated with the high-k charge-trapping layer containing 5, 10 and 15% of np-HfO2 concentration within the SOG-oxide matrix. The memory's charge trapping characteristics are quantized by measuring the flat-band voltage (Vfb) shift of SOHOS capacitors after charge injection and then correlated to np-HfO2 concentration. Since a large memory window has been obtained for our SOHOS memory, the relatively easy injection/annihilation (programming/erasing) of charge injected through the substrate opens the possibility to use this material as an effective charge-trapping layer. A very small injected charge density of 1×10–6C/cm2 shifts Vfb by 100mV without needing to overstress the dielectric by hot-carrier injection, a usual method in SOHOS memories. In conclusion, using a simple spin-coating method for the charge-trapping layer, wide current memory windows have been obtained in SOHOS-memories and their charge-trapping characteristics are quantized and correlated to the np-HfO2. concentration.

Charge trapping behavior in organic–inorganic alloy films grown by molecular layer deposition from trimethylaluminum, p-phenylenediamine and water

Organic–inorganic hybrid or alloy films have great potential as a functional material because they have structural flexibility owing to the presence of an organic moiety. Here organic–inorganic hybrid films were grown by molecular layer deposition (MLD) by using trimethylaluminum and p-phenylenediamine. Although the hybrid films could be grown via the self-limiting growth mechanism of MLD, the hybrid films were severely air sensitive. The stability problem of the hybrid films could be solved by alloying the hybrid layer with Al2O3 layers. The alloy films, which were grown by repeating supercycles with one subcycle for the hybrid layer and four subcycles for the Al2O3 layers, showed excellent dielectric properties: a leakage current density of ∼2.3 × 10−8 A cm−2 at 1 MV cm−1; a dielectric breakdown field at ∼2.9 MV cm−1; and a dielectric constant of ∼6.2. Interestingly, charge trapping behavior was clearly observed in the alloy film. The charge trapping ability of the alloy film was verified with a charge trapping memory capacitor in which the alloy film was inserted as a charge trapping layer.

Organic–inorganic nanohybrid nonvolatile memory transistors for flexible electronics

We report on a low-temperature fabrication of organic–inorganic nanohybrid nonvolatile memory transistors using molecular layer deposition combined with atomic layer deposition. A 3 nm ZnO:Cu charge trap layer is sandwiched between 6 nm tunneling and 20 nm blocking self-assembled organic layers. First, we identify a large memory window of 14.1 V operated at ±15 V using metal–oxide–semiconductor capacitors. Second, we apply the capacitor structure to the nonvolatile memory transistors which operate in the low voltage range of −1 to 3 V. The writing/erasing (+8 V/−12 V) current ratio of ∼103 of the memory transistors is maintained during the static and dynamic retention measurements. The reported organic–inorganic devices offer new opportunities to develop low-voltage-driven flexible memory electronics fabricated at low temperatures.

Comparison of Fluorinated HfO2 and Si3N4 Charge Trapping Layer for Nonvolatile Flash Memories

Characteristics of fluorinated metal/SiO2/HfO2/SiO2/Si (F-MOHOS) and fluorinated metal/SiO2/Si3N4/SiO2/Si (F-MONOS) flash memory using gate fluorine ion implantation (GFI) have been investigated. Since dielectric constant of HfO2 is larger than Si3N4, electric field across on tunneling oxide of F-MOHOS flash memory is larger than F-MONOS flash memory, which results in faster program/erase speed. Moreover, HfO2 exhibits larger effective trapping density than Si3N4, which also contributes to faster program/erase speed for the F-MOHOS flash memory. Besides, charge retention of the F-MOHOS flash memory is superior than the F-MONOS flash memory, primarily due to larger conduction band offset at the HfO2/SiO2 interface (ΔEC = 1.7–2.0 eV) than at the Si3N4/SiO2 interface (ΔEC = 1.1 eV). F-MOHOS flash memory also exhibits superior program/erase endurance than F-MONOS flash memory. Therefore, F-MOHOS flash memory using GFI process is proposed to be suitable for future nonvolatile flash memory applications. On the other hand, larger dielectric constant of HfO2 inevitably induces larger electric field across on blocking oxide of F-MOHOS flash memory, then enhances electron back-tunneling from the gate electrode during erase operation, which results in obvious erase-saturation.

Performance Enhancement of Silicon Nanowire Memory by Tunnel Oxynitride, Stacked Charge Trap Layer, and Mechanical Strain

Heavily doped silicon nanowires (SiNWs) are adopted to fabricate a memory device composed of an AlON tunnel layer and a HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfAlO charge trap bilayer, which exhibits a large memory window of 4.6 V when operated in the program/erase phases, i.e., +12 V for 100 μs and -12 V for 10 ms, along with excellent 70% extrapolated ten-year data retention and good endurance up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> cycles. Strain effects on SiNW memory characteristics have also been investigated. It is demonstrated that the tensile strain increases the program window and the compressive strain improves the data retention. The underlying mechanism is attributed to the incorporation of nitrogen in the AlON tunnel layer.

Investigation of Ti-doped Gd2O3 charge trapping layer with HfO2 blocking oxide for memory application

In this study, Ti-doped gadolinium oxide (Gd2TiO5) is investigated by X-ray diffraction, atomic force microscopy, and capacitance voltage curves (C–V) as the charge trapping layer in metal-oxide-high-k material-oxide-silicon structure memories. It was found that the Gd2TiO5 charge-trapping layer with an HfO2 blocking layer annealed at 900°C had a larger window of 4.8V in the C–V hysteresis loop, a faster program/erase speed and good retention without significant drift up to 104cycles. This excellent performance was attributed to the well-crystallized Gd2TiO5 structure and the higher probability of charges being trapped in the deep trap energy level of the Gd2TiO5. This Gd2TiO5 memory device with post-annealing shows considerable promise for use in future flash memory applications.

Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Charge Trapping Layer

This study investigates the characteristics of the planar twin poly-Si thin film transistor (TFT) EEPROM that utilizes a nitride (Si3N4) charge trapping layer. A comparison is made of two devices with different gate dielectrics, one a 16 nm-thick oxide (SiO2) layer for O-structure and the other 5 nm/10 nm-thick oxide/nitride layers for O/N-structure. Incorporating a nitride charge trapping layer and reducing the tunneling oxide thickness enable the O/N-structure EEPROM to enhance the program/erase (P/E) efficiency. Additionally, EEPROM formed with the tri-gate nanowires (NWs) structure can further enhance P/E efficiency and a large memory window because of its high electric field across the tunneling oxide. Reliability results indicated that, since the nitride layer contains discrete traps, the memory window can be maintained 2.2 V after 10(4) P/E cycles. For retention, the memory window can be maintained 1.9 V, and 30% charge loss for ten years of data storage. This investigation indicates that its possibility in future system-on-panel (SOP) of thin-film transistor liquid crystal display (TFTLCD) and 3-D stacked high-density Flash memory applications.

Fluorinated $\hbox{SrTiO}_{3}$ as Charge-Trapping Layer for Nonvolatile Memory Applications

Charge-trapping properties of SrTiO3 with and without fluorine incorporation are investigated by using an Al/Al2O3/SrTiO3/SiO2/Si structure. The memory device with a fluorinated SrTiO3 film shows promising performance in terms of large memory window (8.8 V) by ±8-V sweeping voltage, large flatband-voltage (VFB) shift (2.5 V) at a low gate voltage of +6 V for 1 ms, negligible VFB shift after 105-cycle program/erase stressing, and improved data retention compared with that with out fluorine treatment. These advantages can be associated with generated deep-level traps, reduced leakage path, and enhanced strength of the film due to the fluorine incorporation.

Concurrent Formation of Blocking-oxide and Charge-trap Layers by Selective Oxidation and Phase Separation of a SiGeO Layer

Concurrent Formation of Blocking-oxide and Charge-trap Layers by Selective Oxidation and Phase Separation of a SiGeO Layer

Covalent Assembly of Gold Nanoparticles for Nonvolatile Memory Applications

This work reports a versatile approach for enhancing the stability of nonvolatile memory devices through covalent assembly of functionalized gold nanoparticles. 11-mercapto-1-undecanol functionalized gold nanoparticles (AuNPs) with a narrow size distribution and particle size of about 5 nm were synthesized. Then, the AuNPs were immobilized on a SiO(2) substrate using a functionalized polymer as a surface modifier. Microscopic and spectroscopic techniques were used to characterize the AuNPs and their morphology before and after immobilization. Finally, a metal-insulator-semiconductor (MIS) type memory device with such covalently anchored AuNPs as a charge trapping layer was fabricated. The MIS structure showed well-defined counterclockwise C-V hysteresis curves indicating a good memory effect. The flat band voltage shift was 1.64 V at a swapping voltage between ±7 V. Furthermore, the MIS structure showed a good retention characteristic up to 20,000 s. The present synthetic route to covalently immobilize gold nanoparticles system will be a step towards realization for the nanoparticle-based electronic devices and related applications.

Metal–Oxide–High-$k$ -Oxide–Silicon Memory Device Using a Ti-Doped $\hbox{Dy}_{2}\hbox{O}_{3}$ Charge-Trapping Layer and $\hbox{Al}_{2}\hbox{O}_{3}$ Blocking Layer

In this paper, we propose Al/SiO2/Dy2O3/ SiO2/ Si, Al/SiO2/DyTixOy/SiO2/Si, and Al/Al2O3/DyTixOy/SiO2/Si as charge-trapping memory devices incorporating high-k Dy2O3 and Ti-doped Dy2O3 films as charge-trapping layers, and SiO2 and Al2O3 films as blocking layers. The Al/Al2O3/DyTix Oy/ SiO2/Si memory device exhibited a larger memory window of ~4.5 V (measured at a sweep voltage range of ±9 V), a smaller charge loss of ~20% (measured time up to 106s and at 85°C), and better endurance (program/erase cycles up to 104) than other devices. These results suggest higher probability for trapping the charge carrier due to the Ti content in the Dy2O3 film, which produce a high dielectric constant and suppress the formation of the Dy-silicate layer, and create a deep trap level in the DyTixOy film.

Charge Storage Characteristics of Si-Rich Silicon Nitride and the Effect of Tunneling Thickness on Nonvolatile Memory Performance

Nonvolatile memory (NVM) devices with nitride-nitride-oxynitride (NNO) stack structure using Si-rich silicon nitride (SiNx) as charge trapping layer on glass substrate were fabricated. Amorphous silicon clusters existing in the Si-rich SiNxlayer enhance the charge storage capacity of the devices. Low temperature poly-silicon (LTPS) technology, plasma-assisted oxidation/nitridation method to form a uniform ultra-thin tunneling layer, and an optimal Si-rich SiNxcharge trapping layer were used to fabricate NNO NVM devices with different tunneling thickness 2.3, 2.6 and 2.9 nm. The increase memory window, lower voltage operation but little scarifying in retention characteristics of nitride trap NVM devices had been accomplished by reducing the tunnel oxide thickness. The fabricated NVM devices with 2.9 nm tunneling thickness shows excellent electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low operating voltage of less than ±9 V and a large memory window of 2.7 V, which remained greater than 72% over a period of 10 years.

Electrical and material characterizations of HfTiO4 flash memory devices with post-annealing

A metal-oxide-high-k HfTiO4-oxide-silicon-type novel nanocrystal memory was fabricated in order to examine temperature-induced effects at different annealing temperatures and find the optimal annealing condition. The material properties and electrical characteristics were investigated via multiple material analysis techniques such as x-ray diffraction, atomic force microscopy, and electrical analysis. Through a thorough study of the crystalline structure, material composition, memory window, and program/erase (P/E) cycle, the optimal annealing temperature at which to deposit a charge trapping layer with excellent material and electrical properties was determined. An HfTiO4 charge trapping layer annealed at 950 °C had a higher window of 5.8 V in the current-voltage hysteresis loop and a higher P/E speed than samples prepared under various annealing conditions. The results indicate that annealing can enhance the crystallization of HfTiO4 and produce a more effective electric field across a tunneling oxide of high quality.