Charge Trap Flash Memory Devices Research Articles

Nonvolatile flash memory device with ferroelectric blocking layer via in situ ALD process

To improve performances of nonvolatile charge trap flash memory devices, we propose an in situ Hf0.5Zr0.5O2 (HZO)/HfO2/Al2O3 stacked structure, which is compatible for Si with the metal–oxide–semiconductor (MOS) process based on all atomic layer deposition. Since the appropriate bandgap difference between Al2O3 and HfO2, stable charge trap operation is achieved. High-quality ferroelectric HZO film characteristics were showed by minimizing defects and Si diffusion through the sub-layer of Al2O3/HfO2. Therefore, HZO as a blocking layer enhances the memory performance of the charge trap structure due to its specific polarization effect. The proposed device has the high polarization characteristics of HZO (2Pr > 20 μ C/cm2) along with a MOS-cap window (>4 V), good retention capability (>10 years), fast program/erase response operation times (<200 μs), and strong durability (>105 cycles) while operating as a form of single level cell. By comparing Al2O3 and ferroelectric HZO as a blocking layer of the charge trap device, we confirmed that the HZO/HfO2/Al2O3 multi-layer structure had excellent characteristics according to various memory performance indicators. Our proposed high-performance charge trap flash memory can be employed in various applications, including Si-based three-dimensional structures with artificial intelligence systems.

String-level compact modeling for dynamic operation and transient analysis of 3D charge trapping flash memory

In this article, we propose a string-level compact model, which is based on accurate and seamless channel electrostatic potential, for dynamic operation of 3D charge trapping flash (CTF) memory. First, we introduce a unit cell model for 3D CTF memory structure based on a conventional BSIM-CMG model using an extended netlist of equivalent circuits which describe the gate-all-around (GAA) structure composed of a metal gate, a blocking oxide, a charge trapping layer, and a tunneling oxide. Then, a string-level compact model is proposed, implying three advantages of inter-cell behaviors, seamless channel potential and process variation. To enhance the accuracy of the model behavior, extended model parameters are extracted showing good agreement with experimental data, such as I-V characteristics, program/erase speed, and incremental step pulse programming (ISPP). Furthermore, to predict channel electrostatic potential more precisely, we verify simulation program with integrated circuit emphasis (SPICE) simulation results of positively and negatively boosted channels comparing them with technology computer-aided design (TCAD) simulation results. Finally, we demonstrate that the proposed model can be efficiently applied to circuit simulation for analysis of the disturbance or failure mechanism and would equip the circuit designers and system architects with an effective tool for design optimization of 3D CTF memory devices.

A triple-level cell charge trap flash memory device with CVD-grown MoS2

This study investigates the triple-level cell (TLC) memory retention of a MoS2-channel based charge trap flash (CTF) device. A top-gated CTF device with a high-κ gate dielectric is found to have a high coupling ratio, which enhances the tunneling efficiency for programming. The fabricated devices show the long memory retention performance for each state, demonstrating the feasibility of a robust TLC CTF memory device based on a CVD grown 2D material.

Impacts of Electrical Field in Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Device

Operation characteristics of polycrystalline germanium (poly-Ge) tri-gate junctionless (JL) charge-trapping (CT) flash memory devices with stacked tunneling layer were studied in this work. The programming speeds of poly-Ge tri-gate JL flash device with GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> tunneling layer are faster than those with GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> or GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ones, thanks to the modified electric field in the tunneling layer. Better retention characteristics are also achieved due to a larger barrier height and physical thickness, because Ge diffusion is effectively suppressed by adding an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> between GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , which can improve the quality of tunneling layer. A poly-Ge CT flash device fabricated with low-temperature process is promising for embedded memory in Ge CMOS or 3D IC.

Implementation of Boolean Logic Functions in Charge Trap Flash for In-Memory Computing

The use of nonvolatile arbitrary logic functions through emerging nonvolatile memory devices has been proposed to implement in-memory computing architecture. Here, in this paper, for the first time, we have proposed a nonvolatile stateful logic methodology based on a charge trap flash (CTF) memory device. Using multi-bit operation, functionally complete Boolean logic functions are experimentally demonstrated. The CTF devices exhibit perfect CMOS compatibility and excellent reliability as compared to other emerging memory devices. In addition, they do not require an additional select transistor, which leads to a more compact array configuration. Our CTF device and operation method may be a promising solution for the hardware implementation of non-von Neumann computing systems.

Electro-Thermal Erasing at 104-Fold Faster Speeds in Charge-Trap Flash Memory

An erasing method capable of speeds 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> -fold faster compared with those by the conventional Fowler-Nordheim (FN) erasing technique is experimentally demonstrated in a gate-all-around junctionless (JL) charge-trap flash memory device using thermal excitation with the aid of electric field. A gate electrode serving as a built-in heater generates Joule heat for thermal excitation of trapped electrons in the charge-trap layer. The electrons excited by thermal excitation are further accelerated for injection into the silicon body by an in-situ applied E-field between the gate and the JL body. Hence, the trapped electrons are removed within 70 ns by electro-thermal erasing.

Fluorine Effects Originating From the CVD-W Process on Charge-Trap Flash Memory Cells

The fluorine (F) effect originating from the chemical vapor deposited (CVD) tungsten (W) process on charge-trap flash memory devices was systematically investigated, and the CVD-W memory was compared with physical vapor deposited (PVD) W memory. The residual F in the CVD-W diffused into Al2O3 and Si3N4 layers, generating shallow charge-trapping sites in each layer. These generated charge-trapping sites were considered to be responsible for the fast-erase and poor-retention characteristics at room temperature in the CVD-W compared to the related characteristics in the PVD-W memory. The generation of charge-trapping sites caused by the residual F in each layer was also supported by the trap density calculation in the Si3N4 and constant current stress test for the Al2O3 layer.

SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices

The SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO2 and Si3N4 layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.

Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices

Charge trapping flash memory devices are susceptible to charge loss mechanisms induced by high energy irradiation such as thermal neutrons, X-rays, and gamma ray. The loss of trapped charges due to charge loss mechanism has resulted in the degradation in data retention performance and unwanted read failures in field applications. In this work, charge loss mechanisms of nanoscale nitride based charge trapping flash memory devices due to irradiation of high energy X-rays were carefully studied and examined. Nitride based charge trapping flash memory device stored charges in the nitride storage layer of an Oxide-Nitride-Oxide stack. Threshold voltage of the nitride based charge trapping flash memory cells were collected before and after X-ray irradiation done onto the memory devices. Threshold voltage distributions have shown that significant number of cells at the lower end of the program distribution had perturbed from the overall distribution that was caused by X-ray irradiation induced charge loss mechanism. In this study, the effect of the use of 300μm Zn filter and its proximity to the device under study to mitigate the X-ray irradiation induced charge loss was also thoroughly elucidated. The results have demonstrated that 300μm Zn filter has significantly improved the immunity of nitride based charge trap flash memory device up to 6.446 times. However, the proximity of the Zn filter to the flash memory device exacerbated up to 7.4280 times due to the impact of secondary effect in X-ray fluorescence to the device under study. Hence, this investigation concluded that X-ray irradiation is a genuine reliability concern for nanoscale nitride based charge trapping flash memory devices. Furthermore, it is recommended to place Zn filter close to X-ray source to significantly mitigate the Vt distribution drift induced by X-ray irradiation.

Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device With Ge Channel

Charge-trapping (CT) flash memory devices with Ge channel are studied for the first time. The operation characteristics of Ge-channel devices with different interfacial layers (IL), including GeO2, GeON, and AlON, are investigated. The programming/erasing speeds of devices with Ge channel can be significantly improved as compared with those with Si or SiGe channel. The retention properties of Ge-channel CT flash devices are much enhanced with a stacked tunneling layer formed by the low-temperature processes. However, the endurance characteristics of Ge-channel devices need improvement as compared with those of Si-channel devices. This may be resolved by a high-quality IL formed with an electron cyclotron resonance system and passivated with a H2 treatment.

Minimized program disturb for vertically stacked junctionless charge-trapping flash memory devices by adopting in-situ doped poly-silicon channel

Effects of in-situ doped (ISD) polycrystalline silicon (poly-Si), which serves as the source, drain and channel, on vertically stacked junctionless (JL) charge-trapping (CT) flash memory devices are investigated for the first time. The vertically stacked JL devices formed by ISD poly-Si channel show minimized program disturb with a large disturb-free window of 4.5V even when a low program-inhibit voltage (Vinhibit) of 6V is applied. It can be attributed to the fast programming speed of ISD JL device. Fast programming/erasing (P/E) speeds, good retention and endurance characteristics are also obtained. Therefore, ISD poly-Si is promising for future three-dimensional (3D) CT flash integration.

Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory

In this work, the origin of the anomalous tail bits have been examined thoroughly on 43nm nitride based charge trap flash memory devices. Tunnel oxide nitridation was implemented on the device under study to enhance its immunity to charge loss mechanism. Due to the extensive program/erase cycling, the increment in the defect density in tunnel oxide layer has generated significant tail bits that exhibited detrimental charge loss at room temperature. The findings have indicated that these tail bits are attributed to randomly distributed defects due to extensive program/erase cycling stress. Furthermore, these tail bits enhanced with longer storage duration at room temperature but deterred at high storage temperature. In this work, the anomalous tail bits were suppressed at high storage temperature. The underlying physical mechanism for these anomalous tail bits was found to be attributed to trap-assisted-tunneling mechanism that enables trapped charges from nitride storage layer to leak out along the vertical path of oxide–nitride–oxide stack of nitrided flash memory. These findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be addressed to achieve desired reliability performance. This work also demonstrated that room temperature storage test is a critical test to investigate the generation of the detrimental anomalous tail bits in reliability characterization and qualification for future nitrided flash memory.

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

Charge Trap Flash (CTF) memory devices, otherwise known as metal-oxide-nitride-oxide-silicon structures, have been the subject of attention in the semiconductor industry due to their advantages over conventional floating gate type memory. These advantages include lower programming voltage, superior programming/erasing speeds, and a simple fabrication process compatible with standard complementary metal-oxidesemiconductor technology [1-3]. Recently, CTF memory devices have gained increasing interest in the three dimensional (3D) integration for next generation nonvolatile memory technology [4,5]. The tunnel oxide thickness plays a crucial role in regulating the erasing speed, data retention characteristics and charge loss mechanisms for CTF memory devices [6], while the thickness of the nitride charge trapping layer is less critical. Nevertheless, in 3D architectures, the nitride thickness has a direct effect on charge storage performance and array density [7]. Moreover, temperatures [8] and trap energy levels [9,10] also are considerable factors for understanding the electron loss mechanisms. Hence, in this letter, Pt/Al2O3/Si3N4/SiO2/Si (MANOS) charge trapping memory capacitors with various thicknesses of nitride layer were fabricated. We investigated and analyzed the effect of nitride thickness, trap energy levels and temperatures on electrons loss behavior in the retention state for MANOS capacitors. Also, a reasonable nitride thickness range was obtained through electrical characteristic measurements. Four charge loss mechanisms [11,12] are involved in the data retention state for scaled CTF memory devices: trapped electrons tunnel from traps to the silicon conduction band (T-B), trapped electrons Zhenjie Tang, Ma Dongwei, Zhang Jing, Jiang Yunhong, and Wang Guixia College of Physics and Electronic Engineering, Anyang Normal University, Anyang 455000, P.R.China

Enhanced Operation Characteristics in Poly-Si Nanowire Charge-Trapping Flash Memory Device With SiGe Buried Channel

Operation characteristics in a polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory device are studied with SiGe buried channel for the first time. Compared with the flash device with a general poly-Si NW channel, the device with SiGe buried channel shows improved programming and erasing speeds since the enhanced electric field in tunneling layer is enhanced by SiGe buried layer. The endurance characteristics are also improved by the SiGe buried channel while retention performances are retained. The SiGe buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Improved Operation Characteristics in Charge-Trapping Flash Memory Devices With Engineered Dielectric Stack, Sige and Junctionless Poly-Si Channels

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Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices

Technology scaling challenges for flash memory beyond 30 nm exacerbated as device fundamental limits are fast approaching. Nitride-based charge trap flash (CTF) is one of the most viable alternatives to eclipse floating gate flash in the market by leveraging the existing materials as compared with other exploratory nonvolatile memory devices. However, postcycled threshold voltage instability in the form of charge loss (CL) mechanisms remains as critical reliability challenges to further improve long-term data retention performance. This paper focuses on long-term data retention reliability issues with an emphasis on major CL mechanisms of nitride-based CTF memory. It encompasses comprehensive reviews and discussions on major CL mechanisms due to intrinsic and extrinsic causes. This paper would serve as a good reference for the future development of nitride-based CTF memory.

(Invited) Improved Operation Characteristics in Charge-Trapping Flash Memory Devices with Engineered Dielectric Stack and SiGe Channel

Programming and retention characteristics of charge-trapping (CT) non-volatile memory (NVM) devices can be enhanced by inserting Al2O3 between Si3N4 and HfO2 as the charge-trapping layer. This is because most of the injecting charges are trapped at Si3N4/Al2O3 interface and Al2O3 also provides a high barrier for electron detrapping. In addition, Compare to those with conventional Si-channel, both programming and erasing speeds are significantly improved by employing a Si0.7Ge0.3 buried channel. Satisfactory retention and excellent endurance characteristics up to 106 P/E cycles with 4.1 V memory window show that the degradation on reliability properties, if it exists, is negligible when SiGe buried channel is introduced.

Performance improvement of metal-Al2O3-HfO2-oxide-silicon memory devices with band-engineered Hf-aluminate/SiO2 tunnel barriers

Physical properties of Hf-aluminate (HA) films with various compositions, deposited by atomic layer deposition, were investigated in terms of microstructure, band-gap, and band-offset with respect to Si. Charge trap flash (CTF) memory devices based on HA/SiO2 stacks as tunnel barriers were also fabricated and characterized. Modulation of HA film composition produced controlled changes of the film's band-gap and band-offset. Additionally, the tunneling efficiency of the HA/SiO2 tunnel barrier stacks was observed to be higher than that for a single SiO2 tunnel barrier, in particular at high voltage bias. The band-engineered CTF memory devices with HA/SiO2 tunnel barriers showed improved program/erase speed compared with those with single SiO2 tunnel barrier. The Al-rich HA/SiO2 tunnel barriers showed a longer charge retention time with superior endurance characteristics; in contrast, the Hf-rich HA/SiO2 tunnel barrier showed degraded charge retention because of current leakage through crystallized regions in the film.

The effect of annealing atmosphere on the (HfO2)0.9(Al2O3)0.1 based charge trapping nonvolatile memory

Charge trapping flash memory devices using (HfO2)0.9(Al2O3)0.1 as the charge trapping layer were fabricated, and the effect of post-annealing atmospheres (NH3 and N2) on its charge storage characteristics was investigated. It was found that NH3 annealed memory device showed a larger memory window of 7.3 V and improved data retention even at 85 °C compared to N2 annealed memory devices. The enhanced memory characteristics should be attributed to deep level bulk charge traps induced in the charge trapping layer by NH3 annealing. In addition, the large conduction band offset value between tunneling layer and charge trapping layer also resulted in good retention performance.

A Four-Bit-Per-Cell Program Method with Substrate-Bias Assisted Hot Electron Injection for Charge Trap Flash Memory Devices

We propose a four-bit-per-cell program method using a two-step sequence with substrate-bias assisted hot electron (SAHE) injection into the charge trap flash memory devices in order to overcome the limitations of conventional four-bit program methods, which use channel hot electron (CHE) injection. With this proposed method, a localized charge injection near the junction edge with an acceptable read margin was clearly observed, along with a threshold voltage difference of 1 V between the forward and the reverse read. In addition, a multi-level storage was easily obtained using a drain voltage step of 1 V at each level of the three programmed states, along with a fast program time of 1 micros. Finally, by using charge pumping methods, we directly observed the detailed information on the spatial distribution of the local threshold voltage in each level of the four states, for each physical bit, as a function of the program voltage.