Charge Trap Flash Memory Research Articles

3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

This paper proposes a synaptic device based on charge-trap flash memory that has good CMOS compatibility and superior reliability characteristics compared with other synaptic devices. Using hot-electron injection and hot-hole injection, we designed operation methods to implement gradual conductance modulation and spike-timing-dependent plasticity. We demonstrate the feasibility of the device for neuromorphic applications through both a device-level technology computer-aided design simulation and a system-level MATLAB simulation. For the first time, we also propose a 3-D stacked synapse array and present the structure, operation, and process methods. The proposed array architecture features a small area and low process cost and could be a novel solution for neuromorphic systems for implementing deep neural networks.

Effect of charge trap layer thickness on the charge spreading behavior within a few seconds in 3D charge trap flash memory

Charge spreading behavior within a few seconds, referred to as early retention, was comprehensively investigated in 24 word-line stacked tube-type 3D NAND flash memory. We thoroughly explored the charge spreading behavior from the perspectives of both electron and hole spreading in 3D NAND flash memory with different charge trap layer thicknesses at various programming and erasing levels for solid and checkerboard patterns to provide guidelines for minimizing and optimizing the charge spreading.

An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches $10^{4}$ .

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel**Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007, the National Key Research and Development Program of China under Grant No 2016YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112.

We propose and investigate a novel metal/SiO2/Si3N4/SiO2/SiGe charge trapping flash memory structure (named as MONOS), utilizing SiGe as the buried channel. The fabricated memory device demonstrates excellent program-erasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of SiGe during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at +11 V for 100 μs. Meanwhile, the memory device exhibits a large memory window of ∼7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s’ retention. In addition, the leakage current density is lower than 2.52 × 10−7 A·cm−2 below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si3N4 charge trapping layer and the better quality of the interface between the SiO2 tunneling layer and the SiGe buried channel. Therefore, the application of the SiGe buried channel is very promising to construct 3D charge trapping NAND flash devices with improved operation characteristics.

Property Improvement of CTF Memories Utilizing Hybrid Tunnel Oxide

Various hybrid tunnel oxides in both MANOS structure and SONOS structure were examined. Among them, SiO2/ZrO2 hybrid tunnel oxide in charge trap flash memory provides promising programming characteristics compared to those of SiO2 tunnel oxide. However, the relatively higher Fowler–Nordheim tunneling barriers for the hole result in insufficient erasing characteristics. In contrast, Si2– X ON X /ZrO2 hybrid tunnel oxide could be erased to negative ${V}_{\textsf {th}}$ . In addition, the retention behaviors of the hybrid tunnel oxides based on an high temperature storage (HTS) test were superior compared to that of SiO2 tunnel oxide. The cycle characteristics in endurance and HTS of Si2– X ON X /ZrO2 hybrid tunnel oxide were confirmed to be better than those of Si2– X ON X tunnel oxide, which implies that they satisfy real operational conditions. Thus, Si2– X ON X /ZrO2 hybrid tunnel oxide can be a promising candidate for a next-generation tunnel oxide.

SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices

The SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO2 and Si3N4 layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (EF) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher EF of MOCVD a-IGZO.

Analysis of Conduction and Charging Mechanisms in Atomic Layer Deposited Multilayered HfO2/Al2O3 Stacks for Use in Charge Trapping Flash Memories

Method for characterization of electrical and trapping properties of multilayered high permittivity stacks for use in charge trapping flash memories is proposed. Application of the method to the case of multilayered HfO2/Al2O3 stacks is presented. By applying our previously developed comprehensive model for MOS structures containing high-κ dielectrics on the J-V characteristics measured in the voltage range without marked degradation and charge trapping (from −3 V to +3 V), several parameters of the structure connected to the interfacial layer and the conduction mechanisms have been extracted. We found that the above analysis gives precise information on the main characteristics and the quality of the injection layer. C-V characteristics of stressed (with write and erase pulses) structures recorded in a limited range of voltages between −1 V and +1 V (where neither significant charge trapping nor visible degradation of the structures is expected to occur) were used in order to provide measures of the effect of stresses with no influence of the measurement process. Both trapped charge and the distribution of interface states have been determined using modified Terman method for fresh structures and for structures stressed with write and erase cycles. The proposed method allows determination of charge trapping and interface state with high resolution, promising a precise characterization of multilayered high permittivity stacks for use in charge trapping flash memories.

The Effect of Thermal Treatment Induced Performance Improvement for Charge Trapping Memory with Al2O3/(HfO2)0.9(Al2O3)0.1/Al2O3 Multilayer Structure

Charge trapping flash memory devices with the structure of [TiN/W]/Al2O3/(HfO2)0.9(Al2O3)0.1/Al2O3/Si were fabricated, and their memory properties were characterized. High-κ (HfO2)0.9(Al2O3)0.1 composite (named as HfAlO in short) was prepared as the charge trapping layer, and the effect of post deposition annealing (PDA) conditions on its charge trapping characteristics was also investigated. The sample treated by high PDA temperature (1000°C) exhibits larger memory window, faster program/erase (P/E) speed, lower P/E voltage, better data retention and endurance performance, which should be ascribed to the intensive mixing of HfO2 and Al2O3 in the charge trapping layer. Therefore, the proposed memory devices show great potential in future nanoscale memory applications.

Improvement of Charge Injection by Using Separated SiN as Charge Trapping Layer in MONOS Charge Trap Flash Memory

The charge trapping characteristics in the metal-oxide-nitride-oxide-silicon memory with separated trapping layer were investigated. Charge injection was enhanced for the reduction of effective oxide thickness of the gate dielectric. High program/erase speed as well as large shift of the threshold voltage were obtained. Charges injection was improved according to the constant current stress measurement. The application of separated charge trapping layer can considerably improve the performance of charge trapping memory.

Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

In this paper, we present the fabrication method of asymmetric independent dual-gate FinFETs with different gate stack using sidewall spacer patterning and two-step chemical-mechanical polishing (CMP) processes. The fin width is controlled as a result of sidewall spacer patterning. The two-step CMP processes are conducted to separate two gates and to make different gate stacks for each gate, respectively. The fabricated devices can be used for multiple applications by utilizing independent two gates. First of all, the independent two gates offer the flexible threshold voltage modulation properties by applying the second gate (G2) bias with little subthreshold swing degradation. Second, the device can be utilized as a charge trap flash memory cell by trapping electrons in the charge storage layer. These results provide a possible way to fabricate asymmetric independent dual-gate FinFETs having potential as a multi-functional single device.

Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices

Charge trapping flash memory devices are susceptible to charge loss mechanisms induced by high energy irradiation such as thermal neutrons, X-rays, and gamma ray. The loss of trapped charges due to charge loss mechanism has resulted in the degradation in data retention performance and unwanted read failures in field applications. In this work, charge loss mechanisms of nanoscale nitride based charge trapping flash memory devices due to irradiation of high energy X-rays were carefully studied and examined. Nitride based charge trapping flash memory device stored charges in the nitride storage layer of an Oxide-Nitride-Oxide stack. Threshold voltage of the nitride based charge trapping flash memory cells were collected before and after X-ray irradiation done onto the memory devices. Threshold voltage distributions have shown that significant number of cells at the lower end of the program distribution had perturbed from the overall distribution that was caused by X-ray irradiation induced charge loss mechanism. In this study, the effect of the use of 300μm Zn filter and its proximity to the device under study to mitigate the X-ray irradiation induced charge loss was also thoroughly elucidated. The results have demonstrated that 300μm Zn filter has significantly improved the immunity of nitride based charge trap flash memory device up to 6.446 times. However, the proximity of the Zn filter to the flash memory device exacerbated up to 7.4280 times due to the impact of secondary effect in X-ray fluorescence to the device under study. Hence, this investigation concluded that X-ray irradiation is a genuine reliability concern for nanoscale nitride based charge trapping flash memory devices. Furthermore, it is recommended to place Zn filter close to X-ray source to significantly mitigate the Vt distribution drift induced by X-ray irradiation.

P-Alloc

Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturbance, and lower access latency. In contrast to conventional planar flash memory, 3D flash memory adopts charge-trapping mechanism. NAND strings punch through multiple stacked layers to form the three-dimensional infrastructure. However, the etching processes for NAND strings are unable to produce perfectly vertical features, especially on the scale of 20 nanometers or less. The process variation will cause uneven distribution of electrons, which poses a threat to the integrity of data stored in flash. This paper present P-Alloc , a process-variation tolerant reliability management strategy for 3D charge-trapping flash memory. P-Alloc offers both hardware and software support to allocate data to the 3D flash in the presence of process variation. P-Alloc predicts the state of a physical page, i.e., the basic unit for each write or read operation in flash memory, and tries to assign critical data to more reliable pages. A hardware-based voltage threshold compensation scheme is also proposed to further reduce the faults. We demonstrate the viability of the proposed scheme using a variety of realistic workloads. Our extensive evaluations show that, P-Alloc significantly enhances the reliability and reduces the access latency compared to the baseline scheme.

Electrical Characteristics of Dual Layered Tunnel Barrier with High Speed and Good Retention for Charge Trap Flash Memory

In this paper, we investigate the electrical characteristics of SiO2/ZrO2 hybrid tunnel oxide in MAONOS structure in an effort to improve program and erase speed as well as retention endurance. Inserting ZrO2 into the conventional MAONOS structure increased the programmed Vth variation to 5.8 V, and increased the erased Vth variation to -3.2 V at 15 MV/cm. The results can be understood in terms of reduced the F-N tunneling barrier due to high-k ZrO2 in the tunneling oxide. In addition, Zr diffusion in SiO2 caused the formation of ZrxSi1-XO2 at the interface region, which reduced the energy band gap of SiO2. The retention property of the hybrid tunnel oxide varied depending on the thickness of SiO2. For thin SiO2 less than 30 Å, the retention properties of the tunneling oxides were poor compared with those of the SiO2-only tunneling oxides. However, the hybrid tunneling oxides with SiO2 thickness thicker than 40 Å yielded improved retention behavior compared with those of the SiO2-only tunneling oxides. The detailed analysis in charge density of ZrO2 was carried out by ISPP test. The obtained charge density was quite small compared to that of the total charge density, which indicates that the inserted ZrO2 layer serves as a tunneling material rather than charge storage dielectric.

Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method

We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport.

Electrical characteristics of SiO2/ZrO2 hybrid tunnel barrier for charge trap flash memory

In this paper, we investigate the electrical characteristics of SiO2/ZrO2 hybrid tunnel oxide in metal–Al2O3–SiO2–Si3N4–SiO2–silicon (MAONOS) structure in an effort to improve program and erase speed as well as retention characteristics. Inserting ZrO2 into the conventional MAONOS structure increased the programmed Vth variation to 6.8 V, and increased the erased Vth variation to −3.7 V at 17 MV/cm. The results can be understood in terms of reducing the Fowler–Nordheim (F/N) tunneling barrier due to high-k ZrO2 in the tunneling oxide. In addition, Zr diffusion in SiO2 caused the formation of ZrxSi1−xO2 at the interface region, which reduced the energy band gap of SiO2. The retention property of the hybrid tunnel oxide varied depending on the thickness of SiO2. For thin SiO2 less than 30 Å, the retention properties of the tunneling oxides were poor compared with those of the SiO2 only tunneling oxides. However, the hybrid tunneling oxides with SiO2 thickness thicker than 40 Å yielded improved retention behavior compared with those of the SiO2-only tunneling oxides. The detailed analysis in charge density of ZrO2 was carried out by ISPP test. The obtained charge density was quite small compared to that of the total charge density, which indicates that the inserted ZrO2 layer serves as a tunneling material rather than charge storage dielectric.

(Invited) Oxide Semiconductor Based Charge Trap Device for NAND Flash Memory

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow 45nm-thick a-IGZO layer on 20nm-thick SiO2/p++-Si substrate, where the 5nm-thick low pressure CVD (LPCVD) SiO2 (tunneling oxide) and 15nm-thick LPCVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of MOCVD and sputtered a-IGZO, faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by X-ray photoelectron spectroscopy and bias-illumination- instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed the higher Fermi level (EF) of the MOCVD a-IGZO (~0.5eV) film compared with the sputtered a-IGZO. Since the programming in flash memory device is governed by the tunneling of electrons from channel to charge trapping layer, the faster programming performance could be the result of higher EF of MOCVD a-IGZO.

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

Operation characteristics of Poly-Si nanowire charge-trapping flash memory devices with SiGe and Ge buried channels

Operation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory devices with a SiGe and a Ge buried channel are studied and compared in this work. The poly-Si NW devices with a Ge buried channel show faster programming and erasing speeds as compared to those with a SiGe one due to a lower energy barrier in tunneling layer with more Ge composition. The retention and endurance characteristics of devices with a Ge buried channel are similar to those with a SiGe one. Ge buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

In this paper, a highly reliable circuit model of gate-all-around (GAA) charge-trap flash (CTF) memory cell is proposed, considering the transient behaviors for describing the program operations with improved accuracy. Although several compact models have been reported in the previous literature, time-dependent behaviors have not been precisely reflected and the failures tend to get worse as the operation time elapses. Furthermore, the developed SPICE models in this work have been verified by the measurement results of the fabricated flash memory cells having silicon–oxide–nitride–oxide–silicon (SONOS). This more realistic model would be beneficial in designing the system architectures and setting up the operation schemes for the leading three-dimensional (3D) stack CTF memory.