Charge Sensitive Amplifier Research Articles

Design and Characterization of a Low-Noise and Low-Background Charge Sensitive Amplifier for the Readout of Germanium Detectors

Design and Characterization of a Low-Noise and Low-Background Charge Sensitive Amplifier for the Readout of Germanium Detectors

Analog Front-End for the Readout of LGAD-Based Particle Detectors

This paper presents an analog front-end channel for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The circuit has been designed in a 65 nm CMOS technology. The charge generated by the detector is integrated by a Charge Sensitive Amplifier (CSA) with dynamic signal compression feature to achieve improved noise performance, along with enhanced time resolution capabilities over the wide range of input charge to be detected (from 45fC to 16pC). An RC-CR shaper with selectable shaping time, a fast discriminator and a Time-to-Amplitude Converter (TAC) complete the readout circuit. An SNR around 300, together with a time resolution of slightly below 60ps, is achieved in post-layout simulations.

Charge-sensitive amplifier design for high-speed interface readout front-end ASICs

The design of Charge-Sensitive Amplifiers (CSAs) and the peaking time impact on high-speed interface readout front-end ASICs for 3D pixel detectors with high timing precision, is addressed in this work. The performance of the CSAs is extracted for several architectures, implemented in 180 nm CMOS, 130 nm SiGe BiCMOS, 65 nm CMOS and 22 nm FD-SOI CMOS process nodes for comparison purposes versus technology scaling. The peaking time, the charge gain, the noise and the bandwidth are simulated for all implemented CSAs, while the best CSA candidate performance-wise for high-speed and high timing precision readout ASICs is designated. Furthermore, a full readout chain, capable of resolving particles with a time precision of <200 ps, is implemented and simulated. The designed readout ASIC exhibits a Time-Walk performance of ≤180 ps, for input charges of 6.3−10ke−, while inducing an equivalent noise charge of ≈570e−.

A low noise capacitance to voltage readout circuit based on active feedback charge sensitive amplifier for micro-gyro.

Trans-impedance amplifier (TIA) based capacitance-voltage (C-V) readout circuits are widely used in micro-machined gyroscopes' control system. In this work, the noise performance of a TIA and charge sensitive amplifier (CSA) based C-V readout circuit is analyzed in detail. The theoretical derivation and simulation experiments carried out in this paper show that the thermal noise of high value feedback resistors in TIA dominates the output noise of the circuit, while a CSA-based readout circuit can overcome this shortcoming. Then, a CSA-based C-V readout circuit is designed with a 1.8V transistor on a 180nm complementary metal-oxide-semiconductor. This C-V-based readout circuit occupies an area of 0.039 mm2, which is smaller than the area of a 0603 package resistor. When 1V bias voltage (Vb) is added to the capacitors under test, the tested C-V gain of this circuit is as high as 225 dB, and the tested output noise of the circuit is less than 150 nV/Hz. Finally, the fabricated chip achieved a resolution of 840 zF/Hz at Vb as low as 1V. This CSA-based C-V readout circuit has more advantages in terms of noise and area over the TIA circuit and is more suitable for integration into the interface integrated circuit for micro-gyroscopes.

Design of a charge-sensitive amplifier for MEMS piezoelectric hydrophone

Hydrophone is an important part of sonar system and convert acoustic signal into electrical signal. However, the electrical signal generated by the hydrophone is relatively weak and cannot be directly used for underwater detection and communication. Therefore, it is necessary to preprocess the generated electrical signal. In this paper, a switched capacitor charge-sensitive amplifier for MEMS piezoelectric hydrophone is designed. In the structure, two single-channel charge amplifiers are used for time-division multiplexing. The noise sampling and charge amplification are performed separately in the same half cycle to achieve the effect of alternating output, thereby increasing the sampling rate and solving the problem of discontinuous output of the switched capacitor circuit. In the circuit design, virtual switch and two-phase non-overlapping clock are adopted to reduce the error caused by charge injection and clock feedthrough effect of CMOS switch. What’s more, the correlated double sampling technique is used to reduce the offset and low frequency noise of the circuit. The gain of the charge-sensitive amplifier designed in this study is 26 dB, the bandwidth is 0.8Hz∼17.6kHz, the equivalent input noise power spectral density is 115.6 nV/Hz at 0.1Hz, and the charge sensitivity is 2 mV / pC. The fitting line between the input charge and the amplitude of the output curve is similar to the theory. The simulation results show that the charge-sensitive amplifier proposed in this study meets the design requirements of the MEMS piezoelectric hydrophone readout circuit.

Circuit design of a novel front readout circuit for SiC neutron detector with leakage current compensation

Radiation detectors have broad application prospects in environmental radiation monitoring, radiation source identification, biomedical imaging, space exploration, astrophysics, other radiation detection and imaging fields. Among the third generation semiconductors, the properties of 4H-SiC are more suitable for making high-temperature and strong radiation neutron detectors. SiC materials have become a current research hotspot. In this paper a special readout integrated circuit is designed for the extremely weak current pulse signal output by SiC trench neutron detector. A leakage current compensation circuit is designed for the influence of leakage current on charge sensitive amplifier(CSA) output baseline. The noise of CSA output is analyzed and the noise minimization is carried out. The circuit can quickly respond to the input signal and extract the energy and time information. The circuit is designed based on the DB Hitek 0.18μm CMOS process model. The layout design is achieved and the post-simulation is completed. Simulated results show that the equivalent input charge range of the system is about 2fC ∼ 20fC. The charge conversion gain is 88mV/fC. The nonlinear error is within 1.6 %. Moreover, the equivalent noise charge is 22e-. The circuit has the advantages of high gain, high linearity and low noise. Therefore, the circuit can effectively adapt to the characteristics of the charge signal output from SiC trench neutron detectors and amplify the output charge signal.

A novel silicon pixel sensor for beam monitoring applications at heavy-ion accelerators

This paper describes a silicon pixel sensor for non-interceptive real-time beam monitoring at heavy-ion accelerators. The total size of the sensor is 4 mm × 5 mm. It has 64 (row) × 120 (column) square pixels, each single of which is in the size of 40 μm × 40 μm. With the exposed sensing pad, this sensor can directly collect the charge in the media over the pixels. The in-pixel circuit mainly consists of a low-noise Charge Sensitive Amplifier (CSA) to establish the signal for the energy reconstruction and a discriminator with a Time-to-Amplitude Converter (TAC) for the Time of Arrival (TOA) measurement. The analog signal from each pixel is accessible through time-shared multiplexing over the entire pixel array. This paper will discuss the design of this IMPix-S1 sensor.

Low-Noise Quality Factor Tuning in Nondegenerate MEMS Gyroscope Without Dedicated Tuning Electrode

Quality factor tuning is attractive in degenerate (DE) and nondegenerate (NDE) MEMS gyros for drift suppression or shock and vibration immunity. This paper proposes three resistance-based Q-factor tuning approaches without dedicated electrodes for NDE gyro. The inherent sensing capacitance is utilized as a Q-tuning mechanism for low C-SWaP (cost, size, weight, and power). Routing traces on MEMS or ASIC chips as well as the input impedance of charge-sensitive-amplifier (CSA) are utilized as damping sources, respectively. The theoretical and experimental results indicate Q-tuning utilizing the CSA's input impedance doesn't deteriorate the gyro's noise floor (ARW = 0.01°/√h, BI = 0.12°/h). Large-scale Q-tuning using the regulation of polarization voltage reduces the sensing Q-factor from 38k to 3k. The gyro's settling time after shock is also reduced from 1.4s to 0.13s after Q-tuning. Besides, a frequency-independent fine Q-tuning using tail current regulation in Opam is proposed to correct the thermal variation of the sensing Q-factor. It improves the gyro's bias drift from 1.5°/s to 0.2°/s. This work presents a low C-SWaP Q-tuning solution for high-end industrial MEMS gyro.

A low-noise, radiation-hardened charge-sensitive amplifier for Silicon carbide neutron detector

Silicon carbide(SiC) neutron detectors can be applied to extreme environments with high temperature and strong radiation. The total noise factor is most significantly influenced by the noise factor of the first stage in a cascade amplifier. Hence, the preamplifier must exhibit exceptional noise performance. The readout circuit is inevitably exposed to the influence of radiation, which may result in temporary or even permanent failure of electronic systems. The connection method between the SiC neutron detector and the readout circuit is typically DC-coupled. When the sensor is working, the leakage current generated by the sensor will enter the input end of the CSA and change the baseline position of the CSA. In this paper, a low-noise CSA with leakage current compensation circuit(LCC) is presented. The circuit’s voltage-to-charge amplification is 2.98mV/fC, and the error due to nonlinearity is below 0.01%. Without considering the input parasitic capacitance, ENC is 43.12e-. In addition, the circuit also has good radiation resistance and leakage current compensation function. It is implemented and simulated in the DB Hitek 0.18μm CMOS process model.

Design and preliminary test results of the charge sensitive amplifier for gain-less charge readout in high-pressure TPC

This paper presents the design and electrical test results of a low-noise front-end chip (named Topmetal-S) in a High-pressure Time Projection Chamber (TPC) for searching the neutrinoless double beta decay. The Topmetal-S has been fabricated in a 130 nm CMOS technology. The proposed front-end chip consists of a charge collection electrode, a Charge Sensitive Amplifier (CSA) and peripheral circuits. The test results indicate that the CSA features an input linear dynamic range of approximately 6.64 fC, a charge-conversion gain of about 220 mV/fC and an Equivalent Noise Charge (ENC) of approximately 115 e - after a digital trapezoidal pulse shaper.

Test measurements of an ASIC for X-ray material discrimination by using on-chip time domain integration and a CdTe sensor

Using time-domain integration (TDI) and a two-dimensional sensor is beneficial for X-ray imaging of moving objects. Applying on-chip instead off-chip TDI decreases the required data throughput between an ASIC and the backend several times [1]. This, in turn, allows us to significantly simplify the ASIC itself as well as the backend.We present the results of test measurements of an ASIC dedicated for X-ray material discrimination by using on-chip TDI and a CdTe sensor.The main part of the ASIC is an 192 × 64 pixel matrix. The pixel size is 100 μm × 100 μm, so the chip size is approximately 6.7 mm × 2 cm. The chip is manufactured in a 130 nm CMOS technology with 8 metal layers. A single pixel analog front-end consists of a charge-sensitive amplifier, a shaper, and three discriminators followed by counters. The test was conducted with a 0.75 mm thick CdTe sensor.First, we show the results of the discriminator offset correction followed by the evaluation of the pixel analog front-end gain and noise conducted with single energy radiation. Next, the results of moving objects imaging are obtained by using an industrial X-ray machine for food inspection (continuous energy spectrum). This is carried out to present an example of the image and evaluate the image signal to noise ratio for different energy discriminator thresholds, sensor bias voltages, detector module temperatures and object speeds.

Lowering the energy threshold using a plastic scintillator and radiation-damaged SiPMs

The radiation damage to a silicon photomultiplier (SiPM) set on a satellite orbit increases energy threshold for scintillator detectors. We confirmed that 1 krad of radiation increases the energy threshold by approximately a factor of 10, which is worst for our system. Using one or two SiPMs damaged by proton irradiation and a plastic scintillator, we performed the following three experiments in our attempt to lower the energy threshold of radiation-damaged SiPMs to the greatest extent: (1) measurements using a current waveform amplifier rather than a charge-sensitive amplifier, (2) coincidence measurements with two radiation-damaged SiPMs attached to one scintillator and summing up their signals, and (3) measurements at a low temperature. Our findings confirmed that the use of a current waveform amplifier, as opposed to a charge-sensitive amplifier and a shaping amplifier, could lower the energy threshold to approximately 65% (from 198 keV to 128 keV). Furthermore, if we set the coincidence width appropriately and sum up the signals of the two SiPMs in the coincidence measurement, the energy threshold could be lowered to approximately 70% (from 132 keV to 93 keV) with little loss of the acquired signal, compared to that of use of only one scintillator. Finally, if we perform our measurements at a temperature of −20 °C, we could lower the energy threshold to approximately 34% (from 128 keV to 43 keV) compared to that of at 20 °C. Accordingly, we conclude that the energy threshold can be lowered to approximately 15% by using a combination of these three methods.

X-ray single photon detection with XPOL-III

XPOL-III is a newly developed CMOS ASIC simultaneously working for collecting charge and processing signals inside Gas Pixel Detectors (GPD). Starting from the architecture of the XPOL ASIC and its successful operation in the IXPE space mission, we implemented specific design changes aiming at increasing the rate capability and the uniformity of response.XPOL-III includes more than 100k pixels at 50 μm pitch in a total active area of about 15 × 15 mm2. Each pixel acts as a charge-collecting anode and is connected to its charge-sensitive amplifier, followed by a shaping circuit and a sample-and-hold system. The chip, like its predecessor, provides self-triggering capability, with automatic localization of the region of interest (ROI) to be readout for each single photon. A new programmable definition of the margin pixels around the ROI was implemented to reduce readout time. Other improvements include the sensitivity of the trigger electronics and an increase in the maximum speed for the serial event readout.In this work we describe the design of this new ASIC and the results of its preliminary tests, in particular in the context of the gas detector application, in which imaging the photoelectron track emitted by single X-ray absorption allows us to measure beam polarization together with timing, imaging, and spectroscopy.

Characterization results of the first small pixel high rate (SPHIRD) pixel detector prototypes

This work presents a summary of the experimental results and the performance obtained from a first set of p-type silicon SPHIRD prototypes. The SPHIRD project (Small Pixel High Rate photon counting Detector) targets a new generation of X-ray photon counting hybrid pixel detectors for synchrotron radiation applications, with small pixels and operating between 10 and 30 keV. The readout ASIC is designed to explore techniques that boost the count rate capabilities of the detector and methods to manage, or in some cases exploit, the effects of charge sharing that are unavoidable with small pixels in this type of detector.The achievement of high photon rates relies on the implementation of a fast charge-sensitive amplifier in the pixelin combination with pile-up compensation techniques, which have been compared experimentally. The obtained results show and quantify their effectiveness in increasing the count-rate handled by the detector.The readout chip also includes dedicated circuitry for the relocation of photon hits, a functionality necessary to reduce the photon losses that are observed in photon counting detectors due to charge sharing when the discrimination threshold is set to 50% of the photon energy. The circuitry is however not limited to full pixel relocation: it also implements resources to reassign X-ray hits within regions smaller than the physical pixel. All these operation modes were experimentally evaluated with a pencil beam and with full field images.

SpacePix3: SOI MAPS detector for space radiation monitoring

The SpacePix3 monolithic active pixel sensor is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The detector is capable of detecting and differentiating protons, electrons, and heavy ions. Its active sensor area is 3.84×3.84 mm2, pixel matrix is arranged in a 64×64 square array with 60 µm pitch. The pixel front-end amplifier signal range is 1–80 ke-, extended up to 30 Me- using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at -150 V, creating a depleted layer approximately 35 µm deep. Impinging particle generates a charge pulse converted to a voltage pulse by the charge-sensitive amplifier. Maximum voltage memorized by the peak detector hold circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total current consumption is 31 mA from a 1.8 V power supply in the SPI mode.

Radiation-hardened-by-design preamplifier with binary weighted current source for radiation detector

This paper presents a radiation-hardened-by-design preamplifier that utilizes a self-compensation technique with a charge-sensitive amplifier (CSA) and replica for total ionizing dose (TID) effects. The CSA consists of an operational amplifier (OPAMP) with a 6-bit binary weighted current source (BWCS) and feedback network. The replica circuit is utilized to compensate for the TID effects of the CSA. Two comparators can detect the operating point of the replica OPAMP and generate appropriate signals to control the switches of the BWCS. The proposed preamplifier was fabricated using a general-purpose complementary metal-oxide-silicon field effect transistor 0.18 μm process and verified through a test up to 230 kGy (SiO2) at a rate of 10.46 kGy (SiO2)/h. The code of the BWCS control circuit varied with the total radiation dose. During the verification test, the initial value of the digital code was 39, and a final value of 30 was observed. Furthermore, the preamplifier output exhibited a maximum variation error of 2.39%, while the maximum rise-time error was 1.96%. A minimum signal-to-noise ratio of 49.64 dB was measured.

SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods

This paper presents the design and measurement results of a prototype SPHIRD-1 ASIC in the CMOS 40 nm process. The chip is dedicated to high count rate single photon counting operation at the European Synchrotron Radiation Facility with Extremely Brilliant Source. The core of the prototype IC is the matrix of 64 32 pixels of 50 μm pitch. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and a detector leakage current compensation circuit. The CSA is connected to a set of three discriminators. The readout channel is equipped with additional circuits, which provide different pulse pile-up compensation methods. The priority of the analog front-end electronics is to process the input signal in a short time (the CSA output pulse time width is only 18 ns) and to keep low noise (the equivalent noise charge at the level of 188 el. rms) with a power consumption equals to 26 μW/pixel. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. The measurements prove the possibility of counting up to 11.5 Gcps/mm2 based on a 10% dead time loss input rate parameter.

Design and Testing of a Prototype ASIC for the MTPC Readout at CSNS Back-n White Neutron Source

In this paper, a prototype Application Specific Integrated Circuit (ASIC) for the Multi-purpose Time Projection Chambers (MTPC) at Back-n White Neutron Source is presented. The ASIC integrates 16 readout channels and is fabricated in a 0.18 μm CMOS process. Each channel consists of a Charge Sensitive Amplifier (CSA), a Pole-Zero Cancellation (PZC), two bridged-T shapers, a baseline holder, and a fully differential output buffer. It provides selectable charge ranges of 2 pC and 10 pC, programmable peaking times from 110 ns to 1 μs, and an adjustable output common-mode voltage from 0.7 V to 1.25 V. The ASIC has already been tested and all the results meet the requirements. In the case of 100 pF input capacitance, 2 pC charge range, and 1 μs peaking time, it features a maximum Integral Non-Linearity (INL) of 0.48% and an Equivalent Noise Charge (ENC) of 0.749 fC, which makes the Signal-to-Noise Ratio (SNR) at full-scale input over 2600. In particular, a crosstalk rejection ratio of 63 dB is obtained in this prototype ASIC by using the baseline holder circuit in each channel to generate references for single-ended to differential conversion, isolating noise and crosstalk from the reference path.

Hybrid SiC Pixel Detector for Charged-Particle Beam Monitor

We report on the hybrid SiC pixel detector for charged-particle beam monitors in high-energy physics experiments. To demonstrate comparable performances of the state-of-the-art Si pixel detectors, SiC pixel sensors with a die size of 25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were fabricated based on the p-n diode structure. We combined 12 × 12 diodes of a pixel size of 160 μm and 270 μm pitch with the dedicated readout ASIC by In/Au stud-bump technology. The front-end chip was designed in 0.35 μm CMOS technology, with consideration of a hybrid configuration. Each pixel circuit consists of a charge-sensitive amplifier and band-pass filter, optimized for the SiC sensor. The low noise performance achieved an equivalent noise charge of 55 ± 5e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–</sup> (rms). The spectrum of <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">241</sup> Am shows an energy resolution of 1.72 keV (FWHM) at 17.8 keV γ-rays at room temperature. The obtained image with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">90</sup> Sr is a proof of a single MIP detection capability with all pixels. Those results prospect a future application of the SiC pixel sensors to high-intensity proton extinction monitors in the COMET muon experiment at Japan Proton Accelerator Research Complex.

A Charge Sensitive Amplifier in a 28 nm CMOS Technology for Pixel Detectors at Future Particle Colliders

This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out by specific front-end chips, typically including a CSA exploited for charge-to-voltage conversion of the signal delivered by the sensor. The main analog performance parameters of the CSA, also referred to as the pre-amplifier, are assessed here by means of specific Spectre simulations, which are meant to evaluate the behavior of the analog processor in terms of noise, linearity and capability to compensate for very large detector leakage currents. Noise simulations revealed an equivalent noise charge close to 75 electrons rms for typical operating conditions. Up to 50 nA sensor leakage current can be compensated for thanks to the CSA Keummenacher feedback network. The total current consumption of the CSA is close to 2.2 µA, which, together with a power supply of 0.9 V, translates to a power consumption of 2.0 µW.