Charge-sensitive amplifier design for high-speed interface readout front-end ASICs

Abstract

The design of Charge-Sensitive Amplifiers (CSAs) and the peaking time impact on high-speed interface readout front-end ASICs for 3D pixel detectors with high timing precision, is addressed in this work. The performance of the CSAs is extracted for several architectures, implemented in 180 nm CMOS, 130 nm SiGe BiCMOS, 65 nm CMOS and 22 nm FD-SOI CMOS process nodes for comparison purposes versus technology scaling. The peaking time, the charge gain, the noise and the bandwidth are simulated for all implemented CSAs, while the best CSA candidate performance-wise for high-speed and high timing precision readout ASICs is designated. Furthermore, a full readout chain, capable of resolving particles with a time precision of <200 ps, is implemented and simulated. The designed readout ASIC exhibits a Time-Walk performance of ≤180 ps, for input charges of 6.3−10ke−, while inducing an equivalent noise charge of ≈570e−.