Charge Sensitive Amplifier Research Articles

Detectors for alpha particles and X-rays operating in ambient air in pulse counting mode or/and with gas amplification

Ionization chambers working in ambient air in currentdetection mode are attractive due to their simplicity and low cost andare widely used in several applications such as smoke detection,dosimetry, therapeutic beam monitoring and so on. The aim of this workwas to investigate if gaseous detectors can operate in ambient air inpulse counting mode as well as with gas amplification whichpotentially offers the highest possible sensitivity in applicationslike alpha particle detection or high energy X-ray photon or electrondetection.To investigate the feasibility of this method two types of open- endgaseous detectors were build and successfully tested. The first onewas a single wire or multiwire cylindrical geometry detector operatingin pulse mode at a gas gain of one (pulse ionization chamber). Thisdetector was readout by a custom made wide -band charge sensitiveamplifier able to deal with slow induced signals generated by slowmotion of negative and positive ions. The multiwire detector was ableto detect alpha particles with an efficiency close to 22%. The secondtype of an alpha detector was an innovative GEM-like detector withresistive electrodes operating in air in avalanche mode at high gasgains (up to 104). This detector can also operate in a cascadedmode or being combined with other detectors, for example withMICROMEGAS. This detector was readout by a conventional charge-sensitive amplifier and was able to detect alpha particles with 100%efficiency. This detector could also detect X-ray photons or fastelectrons. A detailed comparison between these two detectors is givenas well as a comparison with commercially available alphadetectors. The main advantages of gaseous detectors operating in airin a pulse detection mode are their simplicity, low cost and highsensitivity. One of the possible applications of these new detectorsis alpha particle background monitors which, due to their low cost canfind wide application not only in houses, but in public areas:airports, railway station and so on.

Variation and mismatch effects of the low-temperature poly-Si TFTs on the circuit for the X-ray active matrix sensor

The application of the capability of low-temperature poly-Si TFT circuits for high resolution X-ray active matrix sensor is explored. The integration of poly-Si TFT circuits on the glass enables an easy connection for the sensor array with fine pixel pitch. A novel charge sensitive amplifier circuit employing poly-Si TFTs is proposed for the readout system of the active matrix sensor. It can considerably increase the circuit’s immunity to the unavoidable threshold voltage variations of the poly-Si TFTs. The V TH mismatch effect of the TFTs, which results in the offset voltage of the charge amplifier, can also be suppressed by the proposed circuit. However, the noise arisen from the V TH mismatch can be even larger than that from the V TH variation after compensation. It reflects that, for higher bit digital X-ray image sensors, the mismatch effect of the devices must be properly taken into consideration.

Pole-Zero Cancellation Circuit With Pulse Pile-Up Tracking System for Low Noise Charge-Sensitive Amplifiers

Modern X-ray imaging systems require low noise high-count-rate multichannel front-end electronics. Such systems widely use charge-sensitive amplifiers (CSA) with pole-zero cancellation (PZC) circuits for sensor readout. CSAs in multichannel ASICs often include continuous reset systems based on MOS transistors discharging the integrating capacitance. Noise requirements for such front-end electronics put the effective CSA feedback resistance in the range of hundreds of MOmega. On the other hand, the high input pulse rate generates a dc voltage shift at the CSA output that modifies the CSA feedback resistance and degrades the PZC circuit performance. In the paper we analyze these problems and propose a novel circuit solution to bias transistors in the CSA feedback and in the PZC circuit. This bias circuit tracks the above mentioned voltage shift at the CSA output and ensures proper cancellation of the CSA feedback pole even in the case of high rates of input pulses. We present measurements of a test structure for the continuous CSA feedback discharge and implementation of this circuit in a fast multichannel ASIC manufactured in the 0.35 mum CMOS technology. The circuit performance for the high input pulse rate is described in detail.

Noise optimised charge-sensitive CMOS amplifier for capacitive radiation detectors

A low-voltage, low-noise, charge-sensitive preamplifier (CSA) for particle tracking using a silicon strip detector was designed. The preamplifier was optimised in terms of the total output noise performance using a noise minimisation technique based on the MOSFET noise small signal equivalent circuit and readout front-end noise optimisation criteria valid in the strong inversion region. The preamplifier was designed and fabricated in a 0.35 m CMOS process by Austria Mikro Systeme for a specific silicon strip detector of 2 pF capacitance for X-ray spectroscopy. The circuit exhibits satisfactory performance compatible to the specific low-energy radiation detection application. Particularly, the CSA provides an equivalent noise charge of 254 e + 13.5+e - /pF, consumes 165 muW and achieves an output conversion gain equal to 2.81 mV/fC and a linearity <0.57 . Analysis is supported by extensive measurement results confirming the circuit characteristics and their flexibility to be used in a variety of readout applications.

Measurements of Matching and High Count Rate Performance of Multichannel ASIC for Digital X-Ray Imaging Systems

We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3900 times 5000 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel-to-channel (sd/mean ap 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals.

A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology

A new concept for monolithic pixel detector with 100% fill-factor is presented. The detection is based on the charge collection in the depleted zone of the reverse biased diode. Complex pixel electronics, including charge sensitive amplifier, amplitude discriminator and digital storage element is placed completely inside the diode cathode (N-well). A test chip that comprises a small pixel matrix and test structures has been fabricated in a 0.35 μ m high-voltage CMOS process and successfully tested. The results of the electrical tests and measurements with X-ray and beta radioactive sources are presented.

Development of a low-noise analog front-end ASIC for CdTe detectors

This paper describes the recent development of a low-noise analog front-end ASIC for CdTe detectors. The ASIC is designed on the basis of the Open-IP LSI project led by JAXA and implemented using TSMC 0.35- μ m CMOS technology. The ASIC contains eight identical channels, each of which includes a charge-sensitive amplifier, band-pass filters, and a sample-and-hold circuit. Preliminary testing of the ASIC achieved noise performance of 188 e - + 7.5 e - / pF . In order to verify the low-noise characteristics, the ASIC was connected to a guard-ring-equipped CdTe diode detector with dimensions of 2.4 × 2.4 mm and having a thickness of 0.5 mm. As a result, the gamma-ray spectra of radioactive sources were obtained with good energy resolutions of 2.51 and 2.35 keV (FWHM) for gamma rays of 59.5 and 122 keV, respectively, at room temperature.

Response of a pentagonal PZT element as a component of a 4π-real-time detector

The detector characteristics of a pentagonal element were studied by colliding it with hypervelocity micro-particles. A charge-sensitive amplifier was developed for the element of its capacitance ∼10 nF. The output amplitudes were expressed as a linear function of the momentum at collision. Empirical formulas obtained from on-ground experiments could be used for the calibration of the detector. The pentagonal element was potential to measure the momentum during collision from the output amplitude. A set of electrodes on the surface was used to confirm the measurement of the coordinates at collision. A possible application of this pentagonal element on a real-time dust detector was discussed.

Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times

The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor operating in the moderate inversion region is discussed. The MOS transistor operation in the moderate inversion region becomes especially important in multichannel readout systems where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the voltage noise of the input MOS transistor. We carried out noise minimization for such a CSA, searching for an optimum input transistor width. The analyses were made using a simplified EKV model and were compared to HSPICE simulations using a BSIM3v3 model. We considered several CMOS technology generations with minimum transistor gate length ranging from 0.13 mum to 0.8 mum. We studied the sensitivity of ENC to the input transistor width, and propose a simple formula to estimate the optimum transistor width, which is valid in a wide current density range.

Resolution Limits in 130 nm and 90 nm CMOS Technologies for Analog Front-End Applications

In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology generation, to implement readout integrated circuits for future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on two CMOS commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Initial performance of the two-dimensional 1024-channel amplifier array

This paper describes the initial performance of a two-dimensional analog ASIC that has been developed to read out CdTe pixel detectors for the next-generation hard X-ray imager. The readout chip consists of a 32 × 32 matrix of identical 200 μ m × 200 μ m pixel cells. Each readout cell contains a low noise charge-sensitive amplifier, three-stage pulse shaping amplifiers and a comparator circuit. Pulse processing circuits have been also designed to achieve lower power consumption for the space application. Analog outputs by injecting a test pulse have been obtained from 991 pixels out of 1024 pixels. The mean noise level is 297 ± 29 electrons (rms) and power consumption is 110 μ W / pixel .

Counting and Integrating Readout for Direct Conversion X-ray Imaging: Concept, Realization and First Prototype Measurements

A novel signal processing concept for X-ray imaging with directly converting pixelated semiconductor sensors is presented. The novelty of this approach compared to existing concepts is the combination of charge integration and photon counting in every single pixel. Simultaneous operation of both signal processing chains extends the dynamic range beyond the limits of the individual schemes and allows determination of the mean photon energy. Medical applications such as X-ray computed tomography can benefit from this additional spectral information through improved contrast and the ability to determine the hardening of the tube spectrum due to attenuation by the scanned object. A prototype chip in 0.35-micrometer technology has been successfully tested. The pixel electronics are designed using a low-swing differential current mode logic. Key element is a configurable feedback circuit for the charge sensitive amplifier which provides continuous reset, leakage current compensation and replicates the input signal for the integrator. This paper will discuss measurement results of the prototype structures and give details on the circuit design

A multi-channel integrated circuit for use in low- and intermediate-energy nuclear physics—HINP16C

The design, simulations, and tests of a 16-channel chip for solid-state detectors are presented. The chip produces sparsified pulse trains for both linear (pulse height) and timing (relative to an external reference) and allows the use of one of two internal charge sensitive amplifiers or an external amplifier. A shaper and peak detector are implemented in the linear branch and a pseudo-constant fraction discriminator and time-to-voltage converter are implemented in the logic/timing branch. The internal plus external gain options and the preparation of both pulse height and timing pulse trains suitable for pipeline ADCs, makes the chip suitable for a wide variety of applications. The chip was fabricated in the AMI 0.5 μm n-well (C5N) process available through MOS implementation services (MOSIS).

Electrodeposited Micro-Actuators A Simple Tool for Impedance-Based Sensing

This paper is focused on the design of metal (Ni) electro- thermal micro-actuators, fabricated via a single electro- plating step. Analytical and finite-element solutions of the electro-thermal and thermo-elastic problems are presented to aid in the design of the devices. A separate section is devoted to the problem of displacement determination using charge sensitive amplifiers for high-precision capacitance measurements. Finally, a possible future use of these actuators in impedance-based biosensors is outlined.

Low Noise Junction Field Effect Transistors in a Silicon Radiation Detector Technology

We report on n-channel Junction Field Effect Transistors fabricated on high resistivity silicon by means of a specially tailored radiation detector technology. This research activity is being carried out in the framework of a project aiming at the integration of read-out circuits in the same detector substrate. Possible applications are in the field of medical/industrial imaging, space and high energy physics experiments. The pre-existent fabrication process has been modified in several respects to enhance the device noise behavior. In particular, the new process features a high-energy (1 MeV) Boron implantation to obtain a deep p-well which ensures an effective isolation of the transistor from the substrate and a strong modulating effect on the current. Selected results from the experimental characterization of transistors and charge sensitive amplifiers are presented, showing a sizable enhancement in the noise performance with respect to previously available devices

Design of low noise charge amplifier in sub-micron technology for fast shaping time

A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13?m to 0.8?m and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width.

Design and characterization of novel read-out systems for a capacitive DNA sensor

This paper presents novel read-out electronic systems for a fast DNA label-less detection. The capacitive shift due to the hybridization effect is monitored by means of a charge sensitive amplifier and a differential stage. The systems provide an A/D conversion and an evaluation of the capacitive shift amount with a resolution of 11 bit. The read-out solutions demonstrate the ability to identify a 0.01% variation on the capacitive value of the sensor. The investigated techniques are suitable for monolithic systems or for a micro-fabricated array of sensors.

Optimized readout methods of silicon drift detectors for high-resolution X-ray spectroscopy

Silicon Drift Detectors with integrated FET transistor fabricated at Max-Planck-Institute in Munich in cooperation with PNSensor GmbH are widely used as X-ray sensors in many industrial and scientific applications. In the classical readout scheme, the integrated transistor on the SDD is operated in the source–follower configuration. The signal charge is removed continuously by the detector self-rest mechanism. The method gives very good results at counting rates up to 10 kcps. For higher count rates, the FWHM increases with the growing reset current and a slight shift of the energy peak is observed. The relative large signal rise time can be also a limitation for operation at very high count rates. Alternatively, the SDD can be operated in a Charge Sensitive Amplifier (CSA) configuration. The detector signal charge is integrated on a feedback capacitor across an inverting amplifier with the integrated FET as the input transistor. The signal rise time does not depend on the integrated transistor and can be made very short (e.g. 50 ns). In applications requiring very high counting rates and constant energy resolution, pulsed-reset operation of the SDD is desirable. The signal charge is removed by applying short reset pulses to a reset structure integrated on the detector anode. The combination of the CSA readout scheme and the pulsed-reset method allows the operation at the best energy resolution independent on the count rate.

Monolithic pixel detectors in a [formula omitted] CMOS technology with sensor level continuous time charge amplification and shaping

This work studies the feasibility of a new implementation of CMOS monolithic active pixel sensors (MAPS) for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is readout by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, available as a shielding frame for n-channel devices in deep submicron, triple well CMOS technologies. Based on the above concept, a chip, which includes several test structures differing in the sensitive element area, has been fabricated in a 0.13 μ m CMOS process. In this paper, the criteria underlying the design of the pixel level analog processor will be presented, together with some preliminary experimental results demonstrating the feasibility of the proposed approach.

The Hybrid Pixel Sensors and Read-Out Electronics

Hybrid pixel sensors (detectors) have shown to be a valid alternative to other types of Xray imaging devices due to their high sensitivity, linear behavior and wide dynamic range, and low noise. One important feature of these devices is the fact that detectors and readout electronics are manufactured separately. The charge created by the interaction of X-ray photons in the sensor is very small and has to be amplified in a low-noise circuit before any further signal processing. The signal induced on the electrodes of the sensor is transferred to the readout chip, where it is integrated in a charge sensitive amplifier. The issue reviews on physical principles of operation and design of the hybrid pixel sensors developed on the basis of the silicon CMOS and GaAs MESFETtechnologies. The authors have designed GaAs charge sensitive amplifiers for hybrid pixel detectors and show the results of a simulation.