Capacitor Charge Pump Research Articles

A theoretical model for power generation via liquid crystal elastomers

Motivated by the need for new materials and green energy production and conversion processes, a class of mathematical models for liquid crystal elastomers (LCEs) integrated within a theoretical charge pump electrical circuit is considered. The charge pump harnesses the chemical and mechanical properties of LCEs transitioning from the nematic to isotropic phase when illuminated or heated to generate higher voltage from a lower voltage supplied by a battery. For the material constitutive model, purely elastic and neoclassical-type strain energy densities applicable to a wide range of monodomain nematic elastomers are combined, while elastic and photothermal responses are decoupled to make the investigation analytically tractable. By varying the model parameters of the elastic and neoclassical terms, it is found that LCEs are more effective than rubber when used as dielectric material within a charge pump capacitor.

High gain modified SEPIC converter with asymmetrical switched inductor super lift cell for renewable energy applications

ABSTRACT This paper provides a modified single-ended primary inductor converter (SEPIC) with an asymmetrical switched inductor super lift cell (ASISLC) for renewable energy applications. Solar, fuel cells, and so on, provide low output voltage, which is not sufficient for high voltage dc grid or dc loads. Therefore, the existence of a high gain DC-DC converter is mandatory. The proposed converter provides high gain, high efficiency, and less voltage stress at a low duty cycle. The proposed converter incorporates switched inductor together with a super lift cell. The super lift cell has a charge pump capacitor is connected in an asymmetrical fashion. The proposed converter offers continuous current at the input together with the above-mentioned advantages. This paper explains the operation of the ASISLC SEPIC converter in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The operating principle, theoretical analysis, design process, and comparison of the suggested converters with converters from the literature that use similar operating principles are all discussed in this paper. A MATLAB simulation is done and their results are provided. Finally, a hardware prototype for 200W, 50 kHz switching frequency is built and their results are validated to authenticate the effectiveness of the proposed converter.

A Novel High Voltage Gain Buck-Boost Converter with Dual Mode Boost

This paper focuses on introducing a transformerless DC/DC converter with low total switching device power in dual working modes including step-up and step-up/down modes. The proposed converter is analysed in terms of the continuous conduction mode, steady state, and efficiency with the replacement of parasitic resistance effects. The proposed converter in the step-up mode has a high voltage gain ratio and a continuous input current. Then, the other working mode of the proposed converter with relevant DC/DC converters is compared. By this comparison, the proposed converter has a high voltage gain ratio. Also, the converter characteristics such as voltage stress on power switches and charge pump capacitors are in a good condition in this mode. Finally, the experimental results from a laboratory made prototype and the obtained waveforms from the simulation in PLECS are presented for validation such as higher voltage gain ratio, lower total switching device power and better efficiency.  

A Non-Isolated DC-DC Converter with Dual Working Modes and Positive Output Voltage

In this paper, a positive output DC/DC converter with low total switching device power in dual working modes is introduced. One working mode is a step-up mode (boost), and other is a step-up/down mode (buck-boost). The proposed converter in step-up mode has high voltage gain ratio, low stress on switches, and continuous input current. In other working mode, the buck-boost converter with six relevant DC/DC converters is compared. By this comparison, it can be seen that the proposed converter has a lower voltage gain ratio, but instead the converter characteristics such as voltage stress on power switches and charge pump capacitors are in good condition for this mode. The proposed converter is analyzed in terms of the continuous conduction mode (CCM), steady state and efficiency with replacement of parasitic resistance effects. To validate the performance of the proposed converter experiments are conducted in the laboratory to claim the theoretical waveforms obtained from the PLECS simulation.

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit

This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.

Efficient Topology for DC-DC Boost Converter Based on Charge Pump Capacitor for Renewable Energy System

In an attempt to meet the global demand, renewable energy systems (RES) have gained an interest in it due to the availability of the resources, especially solar photovoltaic system that has been an importance since many years because of per watt cost reduction, improvement in efficiency, and abundant availability. Photovoltaic system in remote and rural areas is very useful where a grid supply is unavailable. In this scenario, power electronic converters are an integral part of the renewable energy systems particularly for electronic devices which are operated from renewable energy sources and energy storage system (fuel cell and batteries). In this article, a new topology of charge pump capacitor (CPC) which is based on high voltage gain technique DC-DC boost converter (DCBC) with dynamic modeling is proposed. To testify the efficacy of the introduced topology, a prototype has been developed in a laboratory, where input was given 10VDC and 80VDC output voltage achieved at the load side. Furthermore, the experimental result shows that the voltage stress of MOSFET switches is very less in comparison with the conventional boost converter with the same parameters as the proposed converter.

Single‐stage PFC bridgeless converter

A power factor correction (PFC) charge-pump (CP) bridgeless converter for LEDs is presented. In the input stage, coupled inductors, together with CP capacitors, are integrated into a half-bridge inverter, thus characterising the single stage. This topology even being bridgeless due to the positioning of the load operates with a bus voltage below the bending voltage. The CP configuration is used to reduce the LED's current ripple. The prototype achieves an output power of 60 W with high power factor, achieving the efficiency of up to 94%, 127 Vac input, total harmonic distortion of input current, with harmonic magnitudes within the IEC 61000-3-2 standard class C the device limits and flicker in conformed with the recommendation of IEEE 1789.

An opamp-free second-order noise-shaping SAR ADC with 4$$\times$$ passive gain using capacitive charge pump

This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration on filter capacitors are obviated. It implements 4 $$\times$$ passive gain by capacitive charge-pump techniques that compensates the partial loss of residue voltage and relaxes the specifications of comparator. According to the behavioral modeling and simulation results, an ENOB of 16.88-bit is achieved based on a 10-bit DAC array, at the OSR of 16. Through utilizing the Monte Carlo simulation, the proposed ADC architecture is proven to be a robust system.

A triboelectric nanogenerator energy harvesting system based on load-aware control for input power from 2.4 μW to 15.6 μW

Abstract This paper presents a triboelectric nanogenerator (TENG) energy harvesting system for ultra-low power applications. We propose a load-aware control algorithm to improve the power conversion efficiency as well as the voltage conversion efficiency. The control algorithm minimizes the conduction and switching losses within a switched capacitor charge pump (SCCP) by modulating its switching frequency based on the load condition. Furthermore, a hysteresis input regulation control was developed for preventing breakdown. The overall system was optimized by utilizing a compact spice model from the physical mechanisms of the employed TENG. The fabricated test chip in 65-nm process technology provides a regulated output voltage of 1.2 V with power conversion efficiency of 88% at 30 Hz excitation frequency when the TENG output voltage is 2.5 V.

Integrated Dual Output Converter with Low Electric Stress on Components

In recent days there is a vast development in the field of power electronic converters. Necessity of multiple level of voltage demand is raised for single supply system. To meet different level of load demand single input and multiple output topologies (SIMO) are created. There are many such converters fall under SIMO converters. The Integrated Dual Output Converter (IDOC) is one among them. The IDOC is a DC-DC converter that performs boost and buck operations simultaneously with a single input. It is basically evolved from boost converter, replacing a single switch by couple of switches. Both the switches are connected in series not only to perform both buck and boost operation but also to provide continuous input current. Main advantage of IDOC over conventional boost and buck converter is the reduced number of switches. Comparisons among another six buck-boost converters and the proposed IDOC converter are presented. It is found that the proposed converter’s voltage gain is smaller than the other converters’ in step-down mode. Also, based upon the comparisons among the same kind and same number of components, the voltage and current stresses on the power switch of the proposed IDOC converter are less than or equal to those of the comparative converters, and the voltage stress on the charge pump capacitor and the switching device power rating of the proposed IDOC converter are always lower than those of other comparative converters. These advantages make component selection for the proposed converter much easier, and it can be used for industrial application. In order to check the behavior of the converter simulation is carried out in a MATLAB/SIMULINK. The simulation results validated the operation of the converter.

Analysis and optimization scheme of a 2nd-order passive noise shaping SAR ADC architecture

This paper first reports a specific 2nd order passive noise shaping (NS) successive approximation register analog-to-digital converter (ADC) employing the passive filters and comparator gain techniques (Guo et al. in 2017 Symposium on VLSI circuits, pp C236–C237, 2017). Based on the analysis of the original architecture, a better NS performance can be achieved with zeros and poles optimization through modifying structural parameters. According to the results of behavioral modeling and simulation, the ADC using capacitive charge-pump techniques with improved NTF is shown as follow, which obtained a 17.69 bit effective number of bits. Taking the usefulness of the ADC with optimized NTF into consideration, some Monte Carlo simulations are applied to evaluate its robustness. Finally, the optimized ADC is proven to have a certain stability.

A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

A Novel Buck–Boost Converter With Low Electric Stress on Components

In this paper, a novel buck–boost converter with low electric stress on components and negative output voltage is proposed. The operational principle, steady-state analysis, and small-signal modeling of the proposed buck–boost converter in continuous conduction mode are presented. Comparisons among another five buck–boost converters and the proposed buck–boost converter are presented. It is found that the proposed converter's voltage gain is smaller than the other converters’ in step-down mode. Also, based upon the comparisons among the same kind and same number of components, the voltage and current stresses on the power switch of the proposed buck–boost converter are less than or equal to those of the comparative converters, and the voltage stress on the charge pump capacitor and the switching device power rating of the proposed buck–boost converter are always lower than those of other comparative converters. The efficiency of the proposed buck–boost converter is highest among those converters having the same number of elements. These advantages make component selection for the proposed converter much easier, and it can be used directly in applications needing a negative voltage source. Finally, simulation results and circuit experiments are given for validating the effectiveness of the proposed buck–boost converter.

Ultra‐step‐up dc–dc converter with low‐voltage stress on devices

This study suggests a novel ultra-step-up dc-dc converter with low normalised voltage stress across the power devices. The proposed converter incorporates the conventional boost converter with a self-lift circuit and charge pump concept and utilises a voltage multiplier cell at the output side. In the input side, two inductors are magnetised during the switch on-time. During the switch off-time, the stored energy in these inductors, charge pump capacitor and input source, is delivered to the load. Accordingly, the proposed converter is capable of providing high voltage gains with a small duty cycle. Besides, the voltage stress across the power devices is low. Therefore, the MOSFET switch with low R DS-on and devices with reduced nominal voltage can be used which in turn reduces the conduction and turn-on losses. The analysis of the voltage and current stresses is accomplished. The circuit performance is compared with other solutions in the literature in terms of voltage gain and normalised voltage stress of the semiconductors. Eventually, to validate the theoretical analysis, the experimental results are given.

An Area Efficient Thermal Energy Harvester With Reconfigurable Capacitor Charge Pump for IoT Applications

This brief introduces an integrated energy harvester system targeting Internet of Things sensor applications such as a wireless temperature sensor. The proposed design provides 1-V regulated voltage boosting the input voltage (0.27–1 V) from a thermoelectric generator (TEG). To ensure the maximum power extraction, the proposed energy harvester includes multiple circuit level techniques. First, the reconfigurable capacitor charge pump distributes on-chip capacitors to required step-up stages. This approach optimizes the silicon area by utilizing 100% of on-chip capacitors regardless of charge pump conversion gain. Second, the design is capable of 3-D maximum power point tracking, matching a source impedance to input impedance of the energy harvester. Thus, the proposed design is able to extract power from a small form factor TEG, having low source impedance. The reconfigurable capacitor charge pump has the highest power density while delivering power up to $500~{\mu W}$ . Experimental results show end-to-end power efficiency of 64% @ 1–V output voltage, and an input impedance matching range of $1 {\Omega } - 5~{\mathbf{k}}{\Omega }$ . The energy harvester was fabricated in 130-nm CMOS standard technology with an active area of 0.835 mm2.

An 88% Efficiency 0.1–300-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes

This paper presents a novel 3-D maximum power point tracking (3-D MPPT) system for energy harvesting systems (EHS) within Internet of Things (IoT) smart nodes. The proposed 3-D MPPT utilizes a switch width modulation (SWM) technique for improving power efficiency (PE) at idle ( $\mu \text{A}$ ) and heavy (>300 $\mu \text{A}$ ) load modes. The SWM eliminates the gate driver/conduction loss tradeoff in a reconfigurable switched capacitor charge pump (SCCP). The proposed SWM technique modulates the SCCP switch resistance in proportion to the load condition, input voltage, and $V_{\mathrm {gs}}$ applied. A cold startup technique is incorporated in the proposed EHS with an energy-aware algorithm for input harvester select purpose. The fabricated test chip in 65-nm CMOS technology can harvest solar and thermal energy from 0.35 V and provides a regulated output voltage at 1 V with the peak efficiency of 88% at 200 $\mu \text{W}$ and PE >60% at 100 nW.

Step-Up DC–DC Converters: A Comprehensive Review of Voltage-Boosting Techniques, Topologies, and Applications

DC–DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which fundamental energy storing elements (inductors and capacitors) and/or transformers in conjunction with switch(es) and diode(s) are utilized in the circuit. These techniques include switched capacitor (charge pump), voltage multiplier, switched inductor/voltage lift, magnetic coupling, and multistage/-level, and each has its own merits and demerits depending on application, in terms of cost, complexity, power density, reliability, and efficiency. To meet the growing demand for such applications, new power converter topologies that use the above voltage-boosting techniques, as well as some active and passive components, are continuously being proposed. The permutations and combinations of the various voltage-boosting techniques with additional components in a circuit allow for numerous new topologies and configurations, which are often confusing and difficult to follow. Therefore, to present a clear picture on the general law and framework of the development of next-generation step-up dc–dc converters, this paper aims to comprehensively review and classify various step-up dc–dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc–dc converters are presented and summarized with comparative study of different voltage-boosting techniques.

Analysis of Voltage Doubler Behavior of 2.45-GHz Voltage Doubler-Type Rectenna

This paper describes the voltage doubler (VD) behavior of a 2.45-GHz VD-type rectenna. An important feature of the developed VD-type rectenna is the absence of the charge pump capacitor that is present in conventional VDs. Based on the circuit simulation and measurement results, the developed VD-type rectenna shows drastic improvement to the radio frequency-to-direct current (RF–dc) conversion efficiency in comparison with a half-wave rectifier (HWR)-type rectenna at output loads exceeding $100~\Omega $ . From the simulation, both the VD- and HWR-type rectennas show VD behavior, even without the charge pump capacitor. This behavior was found to be attributable to the electric charge stored in the junction and package capacitances of the Schottky barrier diode in the rectennas. Additionally, it was found that the improvement of the RF–dc conversion efficiency is caused by the voltage conservation in the series diode. This improvement is dependent on the microwave period and the electric discharge time constant. When the microwave period is comparable with the electric discharge time constant, the VD-type rectenna conserves a dc voltage even when the input microwave voltage is negative. These phenomena were observed by analyzing the voltage and current waveforms of the rectenna equivalent circuit obtained via circuit simulation.

Modelling, simulation and experimental investigation of a new two input, series‐parallel switched capacitor converter

A new series-parallel switched capacitor converter topology capable of operating off two independent input sources and generating target output voltage in buck or boost mode is presented. Operation principle, conversion ratios, modelling considerations in different operation modes and extensive loss analysis are derived. The converter is robust and may be operated off one or two input sources, having the ability to change conversion ratio over a wide range. The proposed model assumes that the conduction losses are proportional to the average current flowing through each of the charge pump capacitor in a switching phase. Capacitor current instantaneous waveform in the complete charge, partial charge and no charge modes are captured in simulation and experiment. Model predicted equivalent resistance, output voltage and instantaneous capacitor current waveform concur excellent with simulated and experimental values, rendering the new converter as an excellent candidate for two and single input source applications.

A pipelined SAR ADC with gain-stage based on capacitive charge pump

This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.