Noise Charge Research Articles

Bridging the gap between Monte Carlo simulations and measurements of the LISA Pathfinder test-mass charging for LISA

Context. Cubic gold-platinum free-falling test masses (TMs) constitute the mirrors of future LISA and LISA-like interferometers for low-frequency gravitational wave detection in space. High-energy particles of Galactic and solar origin charge the TMs and thus induce spurious electrostatic and magnetic forces that limit the sensitivity of these interferometers. Prelaunch Monte Carlo simulations of the TM charging were carried out for the LISA Pathfinder (LPF) mission, that was planned to test the LISA instrumentation. Measurements and simulations were compared during the mission operations. The measured net TM charging agreed with simulation estimates, while the charging noise was three to four times higher. Aims. We aim to bridge the gap between LPF TM charging noise simulations and observations. Methods. New Monte Carlo simulations of the LPF TM charging due to both Galactic and solar particles were carried out with the FLUKA/LEI toolkit. This allowed propagating low-energy electrons down to a few electronvolt. Results. These improved FLUKA/LEI simulations agree with observations gathered during the mission operations within statistical and Monte Carlo errors. The charging noise induced by Galactic cosmic rays is about one thousand charges per second. This value increases to tens of thousands charges per second during solar energetic particle events. Similar results are expected for the LISA TM charging.

A readout electronic system for a 3D position-sensitive CdZnTe gamma-ray spectrometer based on the CPRE10-32 readout ASIC

A readout electronic system based on the Charge Pulse Readout Electronics 10-32 (CPRE10-32) Application Specific Integrated Circuit (ASIC) has been developed for the 3D position-sensitive CdZnTe gamma-ray spectrometer. The system includes the Font-end Electrics (FEE) board, the Data Acquisition (DAQ) board, the FPGA firmware, and the PC software. The Full Width at Half Maximum (FWHM) of the electronic noise of the system was approximately 4.72 keV when the 3D-CZT detector and high voltage were connected and the minimum gain was selected. The electronic noise at the minimum and maximum gain using the calibration signal without the detector was approximately 3.335 keV and 3.074 keV, respectively. The Equivalent Noise Charge Number (ENN) was about 375 e- with the detector and about 265 e- with the detector. The test data of Cs-137 demonstrated that the linear response range of the system reached up to 3 MeV and 450 keV at the minimum and maximum gain, respectively. With the 3D-CZT detector, the Am-241 and Cs-137 radioactive sources were detected, and the energy resolution was 7.25% and 2.22%, respectively. By performing electron drift time correction, the energy resolution of the full-energy peak of Cs-137 at 662 keV was improved to 0.76% at medium gain. After acquiring energy and time data successfully, it is demonstrated that this readout electronic system can meet the hardware requirements for Compton scatter imaging with 3D-CZT.

Development of a novel high-performance readout circuit for α and β energy spectrum measurement

A novel high-performance readout circuit with multi-Junction field-effect transistors (Multi-JFETs) and high-speed integrated operational amplifiers as the core was designed. By coupling the circuit to a large area passivated ion injection planar silicon (PIPS) detector, excellent α and β energy spectrum can be obtained. Therefore, it can be applied to radon monitor, radioactive aerosol monitor and other equipment to achieve high precision information on radioactive substances in the environment. The input stage of the circuit adopts the parallel structure of JFETs to achieve the matching between the amplifier circuit with the detector junction capacitance. The bias circuit adopts JFETs to form a constant current source while using the gate-source self-biased parallel structure to obtain large transconductance gain and good amplification linearity. The main amplifier circuit adopts a high-speed and low-noise operational amplifier with the advantages of high open-loop gain and stable quiescent point. The performance of this readout circuit was tested, in which the rise time of the signal is 35 ns, the sensitivity of charge-voltage conversion is better than 0.979 mV/fC when the input capacitance is less than 100 pF, and the equivalent noise charge is 1.55 fC, noise slope is 0.00366 fC/pF. By coupling the readout circuit to a PIPS detector with a sensitive area of 450 mm2, the signal-to-noise ratio of the output signal is 116:1 for the 241Am alpha source and 20:1 for the 90Sr-90Y beta particles. The energy spectrum measurement of the 238Pu source was performed, providing FWHM is 16.90 keV@5499 keV.

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail.The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ∼36mV/ke- when configured in High Gain Mode, and ∼20mV/ke- when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ∼68e-rms and ∼80e-rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ∼ 200ps time bin and the chip can deal with a maximum flux of ∼ 3.6MHzmm−2s−1. In photon counting mode, the chip can deal with up to ∼ 5GHzmm−2s−1.The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

A single hole spin with enhanced coherence in natural silicon

Semiconductor spin qubits based on spin–orbit states are responsive to electric field excitations, allowing for practical, fast and potentially scalable qubit control. Spin electric susceptibility, however, renders these qubits generally vulnerable to electrical noise, which limits their coherence time. Here we report on a spin–orbit qubit consisting of a single hole electrostatically confined in a natural silicon metal-oxide-semiconductor device. By varying the magnetic field orientation, we reveal the existence of operation sweet spots where the impact of charge noise is minimized while preserving an efficient electric-dipole spin control. We correspondingly observe an extension of the Hahn-echo coherence time up to 88 μs, exceeding by an order of magnitude existing values reported for hole spin qubits, and approaching the state-of-the-art for electron spin qubits with synthetic spin–orbit coupling in isotopically purified silicon. Our finding enhances the prospects of silicon-based hole spin qubits for scalable quantum information processing.

On the noise-sensitivity of entangling quantum logic operations implemented with a semiconductor quantum dot platform

A full-stack modeling study is conducted against three types of 2-qubit (quantum bit) entangling logic operations that are implemented with a realistically sized electrode-driven Silicon (Si) quantum dot system. Using device simulations based on the bulk physics augmented with electronic structure calculations based on the effective mass theory, we computationally explore the design of a fast SWAP1/2 (S1/2), Controlled-Z (CZ), and Controlled-X (CNOT) gate, and particularly study their operational sensitivity to the charge noise that is fundamentally not easy to be removed from semiconductors. Our results indicate that a recently reported one-step CNOT logic that is implemented with a single microwave pulse, is much more sensitive to the noise than S1/2 & CZ gate are, recommending basic entangling blocks that would be desirable for designs of quantum circuits based on a Si quantum dot platform.

Devitalizing noise-driven instability of entangling logic in silicon devices with bias controls

The quality of quantum bits (qubits) in silicon is highly vulnerable to charge noise that is omnipresent in semiconductor devices and is in principle hard to be suppressed. For a realistically sized quantum dot system based on a silicon-germanium heterostructure whose confinement is manipulated with electrical biases imposed on top electrodes, we computationally explore the noise-robustness of 2-qubit entangling operations with a focus on the controlled-X (CNOT) logic that is essential for designs of gate-based universal quantum logic circuits. With device simulations based on the physics of bulk semiconductors augmented with electronic structure calculations, we not only quantify the degradation in fidelity of single-step CNOT operations with respect to the strength of charge noise, but also discuss a strategy of device engineering that can significantly enhance noise-robustness of CNOT operations with almost no sacrifice of speed compared to the single-step case. Details of device designs and controls that this work presents can establish practical guideline for potential efforts to secure silicon-based quantum processors using an electrode-driven quantum dot platform.

A novel front-end amplifier for gain-less charge readout in high-pressure gas TPC

This paper presents a novel low-noise front-end amplifier manufactured in a standard 130 nm CMOS process. The front-end amplifier is part of an integrated sensor, with an array of which, forms a charge readout plane in a high-pressure gaseous Time Projection Chamber (TPC) for 0νββ search. The novel front-end amplifier composed of a source-drain follower and a common-source amplifier is proposed. The potential of both the source and drain node of the input transistor follows its gate. Hence the effective input capacitance contributed by the input transistor is significantly reduced. A hexagon charge collection electrode with a diameter of 1 mm is connected to the input node of the front-end amplifier. The shielding technique is applied and the shielding metal is connected to the source or drain node of the input transistor. Therefore, the effective input capacitance contributed by the charge collection electrode is decreased. The extraction result shows that the input capacitance is decreased from the 4 pf down to 7.4 fF. A test chip has been designed and an equivalent noise charge of 33 e− is achieved from the simulations.

Specific Design Features of Charge Sensitive Amplifiers on Arsenide-Gallium Master Slice

For the production of integrated analog circuits with a small-scale integration, which are developed to operate at temperatures up to minus 200 ℃ and/or with absorbed dose of gamma radiation up to 5 Mrad, a gallium arsenide master slice has been created. The following types of active elements are used in this master slice: DpHEMT with gate dimensions 100 ηm/0,2 ηm and 10 ηm/0,2 ηm; p-n-p HBT, they were chosen for realization of most common analog circuits of operational amplifiers, comparators, voltage followers. Despite the small number of available DpHEMT with high transconductance for circuit synthesis and volt-ampere characteristics features of DpHEMT experimental samples, which exclude use of those transistors at low drain current, master slice give opportunity for developing charge-sensitive amplifiers (CSA) circuits with only one type of active elements – DpHEMT. At the same time, correct choice of the operating point of transistors provide development of low-noise, high-speed CSAs with better parameters than silicon CSAs for sensors with internal capacitance up to 100 pF. So, developed on GaAs master slice CSA with head DpHEMTs and ratio of the gate width to its length, equal to W/L = 2000 and W/L = 3000, characterized by current consumption ICC = 5,46 mA and ICC = 5,25 mA, rise time tR = 10,7 ns and tR = 9,6 ns, equivalent noise charge ENC = 3960 el, and ENC = 3700 el. with sensor capacitance of 50 pF, while the CSA with a head silicon p-channel junction field-effect transistor has W/L = 3870, ICC = 6,99 mA, tR = 27,7 ns, ENC = 5360 el. with the same sensor capacitance.

Shelving and latching spin readout in atom qubits in silicon

Singlet-triplet qubits typically require large magnetic field gradients on the order of militeslas to achieve high-fidelity electrically-controlled qubit operations. However, such large magnetic field gradients in quantum dot systems also increase charge noise and provide a relaxation pathway from the triplet to singlet qubit state, making high-fidelity readout challenging. Recently, shelving and latched readout have been employed in gate-defined quantum dots and donor-dot systems to achieve readout fidelities of 80% and 99.86%, respectively. In this paper, we theoretically examine shelving and latched singlet-triplet readout techniques for multidonor-based qubits in silicon where the large phosphorus hyperfine interaction of the order of 100 MHz gives rise to large effective magnetic field gradients (equivalent to tens of mT) but where it can change in time due to the presence of nuclear spin flips. Using numerical simulations, we show that shelving readout does not work giving a zero average visibility for mutidonor quantum dots, due to the time-varying nuclear spin polarization. To remedy this we propose adding a calibration step, in which we derive the nuclear spin polarization from a single shelving readout of a singlet state, before every qubit operation. The derived information can then be used via a feed-forward protocol to apply correct readout mapping, greatly improving the overall readout fidelity to $>99%$. We also simulate the latched readout mechanism, which is resistant to nuclear polarization changes and is thus promising for achieving high visibility readout. Here we observe a nonzero readout visibility irrespective of the nuclear spin flipping. Finally, we discuss how to optimize the readout visibility in the presence of strong hyperfine interactions and show that for both readout methods we can obtain readout fidelity $>99%$. These results demonstrate that singlet-triplet qubits based on multidonor quantum dots are a promising route for future electrically controlled qubits in silicon.

Pauli spin blockade in a resonant triple quantum dot molecule

A Pauli spin blockade in quantum dot systems occurs when the charge transport is allowed only for some spin states, and it has been an efficient tool in spin-based qubit devices in semiconductors. We theoretically investigate a Pauli spin blockade in a triple quantum dot molecule consisting of three identical quantum dots in a semiconductor in the presence of an external magnetic field through the molecule. When the three-electron state is on resonance with two- or four-electron states, the Aharonov–Bohm oscillation and the Zeeman splitting lead to a periodic spin blockade effect. We focus on the spin blockade at a two- and three-electron resonance and show that we can tune the magnetic field to selectively allow only either a spin-singlet or spin-triplet state to add an additional electron from tunnel-coupled leads. This spin blockade maintains the three quantum dots at the optimal sweet spot against the charge noise, demonstrating its potential as an efficient readout scheme for the qubits in quantum dot systems.

A High Time-Resolved Front-End ASIC for APD Array Detector in Nuclear Resonant Scattering Experiments With Synchrotron Radiation

A high time-resolved front-end readout chip has been developed for avalanche-photodiode (APD) array detectors in nuclear resonant scattering (NRS) experiments. The chip has eight channels. Each channel consists of a preamplifier, a voltage discriminator, an open-drain output driver, and a local digital-to-analog converter (LDAC). The application-specific integrated circuit (ASIC) chip has been designed and fabricated in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with a chip size of 1.1 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times2.3$ </tex-math></inline-formula> mm. The electrical characterizations of all eight channels demonstrate good time resolution (TR) (rms) on the output pulse leading edge, with the measurement result better than 25 ps for high input signal charges (>30 fC) and better than 98 ps for low input signal charges (8–30 fC), for an APD sensor capacitance as large as 15 pF. The equivalent noise charge (ENC) received from the measurement can be represented as ENC = 592.4 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> + 50.7 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> /pF. The power consumption is 17.6 mW per channel: 2.7 mW for the preamplifier–discriminator stage and 14.9 mW for the output low-voltage differential signaling (LVDS) driver.

Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology

In this work the initial performance studies of the first small monolithic pixel sensors dedicated to charged particle detection, called CE-65, fabricated in the 65nm TowerJazz Panasonic Semiconductor Company are presented. The tested prototypes comprise matrices of 64×32 square analogue-output pixels with a pitch of 15μm. Different pixel types explore several sensing node geometries and amplification schemes, which allows for various biasing voltage of the detection layer and hence depletion conditions and electric field shaping. Laboratory tests conducted with a 55Fe source demonstrated that the CE-65 sensors reach equivalent noise charge in the 15 to 25e− range and excellent charge collection efficiencies. Charge sharing is substantial for standard diodes, but can be largely suppressed by modifying their design. Depletion of the thin sensitive layer saturates at a reverse diode bias of about 5 V.

An ultra-fast low-noise preamplifier for Low Gain Avalanche Detectors

The Low Gain Avalanche Detector (LGAD) is a novel Silicon detector with precise timing and fast response. To study the transient response of LGADs, we need to obtain the detector signal using Transient Current Technique (TCT), for which a preamplifier with high bandwidth and low noise is required. Currently, the most widely used preamplifier board in the LGAD community is developed by University of California, Santa Cruz (UCSC). In this paper, we will introduce a newly designed LGAD preamplifier board. Compared with the UCSC board, the performance has been fully improved. The board contains a transimpedance amplifier and two-stage voltage amplifiers. The total charge gain of our preamplifier reaches 20.58 mV ns/fC, with good linearity in the input dynamic range of [0.7 fC, 66 fC]. The −3-dB bandwidth is about 870 MHz, meeting the demands of LGAD amplification. We conducted 90Sr β-scope tests using our preamplifiers and HPK 3.1 single sensors. The equivalent noise charge at 20 °C is 0.27 fC. The jitter contributed by our preamplifier is about 7.12 ps. The results show that our single-channel preamplifier has lower noise and better time resolution than the UCSC boards. Besides, a 9-channel preamplifier board is developed for multi-pad LGAD readout. All channels have good uniformity and low noise. Our preamplifier boards can be well applied in β-scope or laser-scanning TCT tests of LGADs.

Low-Frequency Correlated Charge-Noise Measurements Across Multiple Energy Transitions in a Tantalum Transmon

The underlying charge noise mechanisms found in tantalum are experimentally investigated, providing a wealth of information on the technological possibilities of superconducting qubits based on this material.

Enhancement of radiation detection performance with reduction of EH6/7 deep levels in n-type 4H–SiC through thermal oxidation

We report the effect of EH6/7 electron trap centers alone on the performance of high-resolution radiation detectors fabricated on n-type 4H–SiC epitaxial layers. A Schottky barrier detector (SBD) and a metal-oxide-semiconductor (MOS) capacitor detector fabricated using two sister samples derived from the same 50 μm 4H–SiC parent wafer exhibited widely different energy resolutions of 0.4% and 0.9% for 5486 keV alpha particles. An equivalent noise charge model analysis ruled out the effect of the detector capacitance and the leakage current on the resolution of the detectors. Deep level transient spectroscopic studies revealed the presence of two trapping centers in each detector within the temperature scan range 240–800 K. The Z1/2 center, a potential electron trap, was detected in both the detectors in equal concentration, which suggested that the observed difference in the energy resolution is due to the presence of the other defect, the EH6/7 center, in the SBD. The capture cross section of the EH6/7 center was calculated to be three orders of magnitude higher than the second defect [a carbon antisite vacancy (CAV) center] observed in the MOS detector with an activation energy of 1.10 eV, which accounted for the enhanced electronic trapping in the SBD leading to its poor energy resolution. It has been proposed that the EH6/7 centers in the SBD have likely been reconfigured to CAV pairs during the thermal growth of the silicon dioxide layer in the MOS detector. The proposed formation mechanism of CAV, a stable qubit state for quantum information processing, addresses the outstanding questions related to the role of defect dynamics in their formation.

Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor

We propose a hybrid self-curing method based on the parasitic bipolar junction transistor (PBJT) inherent to metal-oxide-semiconductor field-effect transistor (MOSFET). The PBJT utilizes the positive feedback of impact ionization to flow a large current close to the channel, generating Joule heat. Unlike conventional self-curing methods, the PBJT-based self-curing recovers the damaged gate oxide along the lateral dimension of the entire channel. The effects of the hybrid curing are quantitatively verified by low-frequency noise spectroscopy and charge pumping method.

Study and characterisation of pad-based readout for RPC detector

The Resistive Plate Chamber (RPC) is a parallel plate avalanche type particle detector which uses a gas mixture as its active detection medium. While high resistivity materials like glass or bakelite plates are commonly used as the detector electrodes, plastic core-based and metal foil laminated pickup panels with segmented strips are used to readout the induced signals. Large area RPCs (of dimension 2 m× 2 m) of this design are chosen as the active detector elements for the India-based Neutrino Observatory's (INO) magnetised Iron Calorimeter (ICAL) detector. One of the main goals of the ICAL detector is a precision measurement of neutrino oscillation parameters. As part of the ongoing detector R&D, a pad-based — instead of strip-based readout — scheme is being developed to improve localization of particle hit positions, while retaining good charge profile and noise rate characteristics of the strip-based RPC based detectors.

A prototype pixel readout chip working in single photon counting mode with a novel charge sharing suppression scheme

Spectral distortion due to the charge sharing effect becomes a severe issue in single-photon counting pixel detectors. The HEPS-BPIX4 prototype chip, dedicated for the HEPS in China, implements a novel architecture to mitigate charge sharing and permit spectroscopic imaging with high efficiency. In the architecture, a central pixel communicates with others in a cluster of 3 × 3 pixels. The algorithm simulation showed a charge sharing elimination accuracy better than 90%. The prototype chip has been designed in a 130 nm CMOS technology. The preliminary measurements show a charge gain of 48 mV/ke− and an equivalent noise charge of 150 e− rms. Detailed tests in a 4 × 4 pixel array for the charge sharing are performed using electrical test pulses. The hit allocation in the core four adjacent pixels of the array indicates that effective suppression of charge sharing has been realized.

Single-junction quantum-circuit refrigerator

We propose a quantum-circuit refrigerator (QCR) based on photon-assisted quasiparticle tunneling through a single normal-metal–insulator–superconductor (NIS) junction. In contrast to previous studies with multiple junctions and an additional charge island for the QCR, we directly connect the NIS junction to an inductively shunted electrode of a superconducting microwave resonator making the device immune to low-frequency charge noise. At low characteristic impedance of the resonator and parameters relevant to a recent experiment, we observe that a semiclassical impedance model of the NIS junction reproduces the bias voltage dependence of the QCR-induced damping rate and frequency shift. For high characteristic impedances, we derive a Born–Markov master equation and use it to observe significant non-linearities in the QCR-induced dissipation and frequency shift. We further demonstrate that, in this regime, the QCR can be used to initialize the linear resonator into a non-thermal state even in the absence of any microwave drive.