Charge Handling Capacity Research Articles

Current Input Pixel-Level ADC with High SNR and Wide Dynamic Range for a Microbolometer.

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for two-dimensional medium wavelength infrared microbolometer arrays. The signal-to-noise ratio (SNR) and charge handling capacity of the unit cell circuit are improved by using the current input pixel-level ADC. The charge handling capacity of the integrator is appropriately extended to maximize the integration time regardless of the magnitude of the input current and low power supply voltage. The readout circuit was fabricated using a 0.35-μm 2-poly 4-metal CMOS process for a 640 × 512 array with a pixel size of 40 μm × 40 μm. The peak SNR and dynamic range are 77.1 and 80.1 dB, respectively, with a power consumption of 0.62 μW per pixel.

A 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs

A hybrid Analog to digital converter (ADC) is presented for long-wave infrared focal plane arrays. A two-stage quantization structure is applied in the folding integration process, which results in better chargehandling capacity and higher linearity compared with conventional designs while using fewer transistors at the pixel level. By employing a circular-adder-based counting structure with 3T dynamic memory cells, hardware consumption can be reduced. A pixel circuit of pitch 15μm has been designed using the 0.18mm Complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the pixel-level ADC is 0.214μW, and the charge-handling capacity is 1Ge-. Simulation results demonstrate a signal-to-noise ratio of 90dB and a nonlinearity of 0.11%.

Dynamic Capacitance Variations Due to Barrier Modulation in Pinned Photodiode of CMOS Image Sensor

The pinned photodiode (PPD) capacitance is an important parameter in CMOS image sensor design since it provides useful information on the charge handling capacity of the photodiode. The model of the dynamic capacitance of the PPD includes a fixed depletion capacitance and a variable diffusion capacitance. The variable component of the photodiode capacitance is estimated by measuring the feedforward voltage at the floating diffusion node. However, the estimated feedforward voltage is highly nonlinear at its full-well condition. In this article, the transfer gate (TG) channel potential is shown to be dependent on the number of charges integrated in the PPD. The nonlinear behavior of TG channel potential influences the effective potential barrier. The nonlinearity observed in the feedforward voltage is also explained using the nonlinear behavior of TG channel potential. In the literature, the influence of the effective potential barrier on the photodiode capacitance models is not taken into account. In this article, the influence of the effective potential barrier on the full-well capacity, feedforward effect, and PPD capacitance is studied. The improved photodiode capacitance model using the effective potential barrier is in good agreement with the measurement results.

Performance of Hg1−xCdxTe infrared focal plane array at elevated temperature

The simulated optical and electrical performance of the infrared HgCdTe focal plane array (FPA) for elevated operation temperature is reported. The depleted absorber layer is explored for equilibrium mode of operation up to 160 K. A resonant cavity is created to improve photon-matter interaction and hence, reduces the required absorption volume. The volume of the active region of HgCdTe detector is reduced by 70% in this manner. Dark current density is decreased without compromising the quantum efficiency. The effect of the reduced band filling effect leading to higher absorption coefficient and more efficient utilization of incident flux is employed. High quantum efficiency is achieved in a thin compositionally graded n+/ν/π/p HgCdTe photo-diode. This architecture helps to minimize the requirement of charge handling capacity in the CMOS read-out integrated circuit (ROIC) as the operation temperature is increased. Quantum efficiency ∼30% or above is shown to be sufficient for Noise Equivalent Temperature Difference (NETD) less than 20 mK with the reported design.

Dynamic power reduction in digital pixel design for large format focal plane arrays

This paper presents a design and analytical approach to significantly reduce the dynamic power consumption of front-end pixel design for digital readout integrated circuits (DROICs) in digital pixel sensor (DPS) arrays. DPS architecture relies on coarse quantization with pulse frequency modulation (PFM) and a novel approach of extended integration incorporated to achieve lower noise. The design is fabricated in 90nm CMOS process with pixel pitch of 30µm. Proposed architecture can attain eminently high charge handling capacity of 2.2Ge- with a quantization noise of 1072e- and extremely low power dissipation of 14.28mW. The proposed dynamic power reduction paradigm enables to alleviate the overall power consumption to 35% as compared to state-of- art PFM based 256×256 DPS array with the lowest Figure of Merit (FoM) of 297fJ/LSB reported earlier. The power reduction escalates further for higher detector currents and large format Focal Plane Arrays (FPA). The proposed design is tested and compared to our previous DROIC measurement results and other works in terms of power and quantization noise.

Design of current mirror integration ROIC for snapshot mode operation

Current mirror integration (CMI) read out integrated circuit (ROIC) topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30 × 30 μm2 pixel size, 4 × 4 array size, variable frame rate, 5 Mega pixel per second (Mpps). Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of 83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6M UMC 180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.

Digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs)

This paper presents a digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs) with a charge handling capacity of 44.8Me− while achieving quantization noise of 198e− and power consumption of 14.35mW. Conventional pulse frequency modulation (PFM) method is supported by a single slope ramp ADC technique to have a very low quantization noise together with a low power consumption. The proposed digital TDI ROIC converts the photocurrent into digital domain in two phases; in the first phase, most significant bits (MSBs) are generated by the conventional PFM technique in the charge domain, while in the second phase least significant bits (LSBs) are generated by a single slope ramp ADC in the time domain. A 90×8 prototype has been fabricated and verified, showing a significantly improved signal-to-noise ratio (SNR) of 51dB for low illumination levels (280,000 collected electrons), which is attributed to the TDI implementation method and very low quantization noise due to the single slope ADC implemented for LSBs. Proposed digital TDI ROIC proves the benefit of digital readouts for scanning arrays enabling smaller pixel pitches, better SNR for the low illumination levels and lower power consumption compared to analog TDI readouts for scanning arrays.

Design of High-Precision ROIC for Quantum Dot Infrared Photodetector

Read out integrated circuit (ROIC) design for quantum dot infrared photodetector (QDIP) array requires large charge handling capacity, low readout noise, minimum detector bias voltage variations, and minimum power dissipation. ROIC design for such applications is challenging due to complex requirements and often needs iterative fabrications to meet all requirements. In this letter, we propose a decision matrix-based optimization method for large dynamic range ROIC implementation. The optimization method is based on trade off analysis, design, and simulation of identified ROIC parameters. This methodology has been applied to an actual case, and the optimum ROIC topology was selected using the optimization method described in this letter. The critical specifications are charge handling capacity of greater than 5 $\text{M}\overline {e}$ and low readout noise of less than 600 electrons, in 180-nm CMOS process. The large dynamic range ROIC consists of a charge integration stage, charge to voltage converters, correlated double samplers, sample and holds, column amplifiers, analog multiplexer, and a buffer amplifier stage. This letter also highlights the measured test chip results of an ROIC array of 30 $\mu \textrm {m} \times 30~\mu \text{m}$ pixel size, in which we have been able to achieve a charge handling capacity of 9.8 $\text{M}\overline {e}$ and the noise of 350 electrons.

Temperature Effects on Feedforward Voltage in Standard CMOS Pinned Photodiodes

The dynamic range and the signal-to-noise ratio of a CMOS image sensor depend on the saturation level of the photodiodes. A very high charge handling capacity or the full well of the photodiode is desired. The thermionic emission of the electrons from the photodiode to the collection node of the pixel reduces the full well capacity of the photodiode. The effect of operating temperature on this thermionic effect on full well capacity is studied in this paper. As the temperature increases, electrons gain thermal energy and are able to overcome the potential barrier between the photodiode and the collection node. This is observed as an increased feedforward voltage. The feedforward voltage shows a logarithmic relationship with temperature changes. The rate of change of the feedforward voltage is not uniform and depends on the position of the quasi-Fermi level. For lower temperature ranges, the change in the feedforward voltage observed is linear, while, for higher temperature ranges, the change is logarithmic in nature.

Non-linear responsivity characterisation of a CMOS Active Pixel Sensor for high resolution imaging of the Jovian system

The Jovian system is the subject of study for the Jupiter Icy Moon Explorer (JUICE), an ESA mission which is planned to launch in 2022. The scientific payload is designed for both characterisation of the magnetosphere and radiation environment local to the spacecraft, as well as remote characterisation of Jupiter and its satellites. A key instrument on JUICE is the high resolution and wide angle camera, JANUS, whose main science goals include detailed characterisation and study phases of three of the Galilean satellites, Ganymede, Callisto and Europa, as well as studies of other moons, the ring system, and irregular satellites.The CIS115 is a CMOS Active Pixel Sensor from e2v technologies selected for the JANUS camera. It is fabricated using 0.18 μ m CMOS imaging sensor process, with an imaging area of 2000 × 1504 pixels, each 7 μ m square. A 4T pixel architecture allows for efficient correlated double sampling, improving the readout noise to better than 8 electrons rms, whilst the sensor is operated in a rolling shutter mode, sampling at up to 10 Mpixel/s at each of the four parallel outputs.A primary parameter to characterise for an imaging device is the relationship that converts the sensor's voltage output back to the corresponding number of electrons that were detected in a pixel, known as the Charge to Voltage Factor (CVF). In modern CMOS sensors with small feature sizes, the CVF is known to be non-linear with signal level, therefore a signal-dependent measurement of the CIS115's CVF has been undertaken and is presented here. The CVF is well modelled as a quadratic function leading to a measurement of the maximum charge handling capacity of the CIS115 to be 3.4 × 104 electrons. If the CIS115's response is assumed linear, its CVF is 21.1 electrons per mV (1/47.5 μ V per electron).

Extending the dynamic range of fully depleted pnCCDs

pnCCDs are a special type of charge coupled devices (CCD) which were originally developed for applications in X-ray astronomy. At X-ray Free Electron Lasers (XFEL) pnCCDs are used as imaging X-ray spectrometers due to their outstanding characteristics like high readout speed, high and homogeneous quantum efficiency, low readout noise, radiation hardness and high pixel charge handling capacity. They can be used both as single-photon counting detectors for X-ray spectroscopy and as integrating detectors for X-ray imaging with count rates up to 104 photons of 1 keV per pixel and frame. However, extremely high photon intensities can result in pixel saturation and charge spilling into neighboring pixels. Because of this charge blooming effect, spatial information is reduced. Based on our research concerning the internal potential distribution we can enhance the pixel full well capacity even more and improve the quality of the image. This paper describes the influence of the operation voltages and space charge distribution of the pnCCD on the electric potential profile by using 2D numerical device simulations. Experimental results with signal injection from an optical laser confirm the simulation models.

A denoising method based on multiple-stage acousto-optic tunable filter in the green laser measurement system

The charge handling capacity of CCD camera is limited, so image distortion is caused by bright light generated by the hot workpiece. The green laser stripe captured by CCD camera is fuzzy in the green laser measurement system. In order to make the image of the stripe clearer, the filter system is designed based on multiple-stage acousto-optic tunable filter. In the filter system, a computational model is built by combining the visible radiation character of hot workpiece and the threshold power density of CCD saturation. The curve of the filtering rate of bright light can be obtained using the computational model. In order to realize the goal of intelligent filter, each stage of the acousto-optic tunable filter is adjusted according to the curve of the filtering rate. Finally, the image of green laser stripe on hot workpiece is clearer. The filter system designed in the paper is viable according to the experiment results. And the accuracy of the green laser measurement system is improved.

A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantization noise

This paper represents a novel digital readout for infrared focal plane arrays with 2.33Ge− charge handling capacity while achieving quantization noise of 161e−. Pixel level A/D conversion has been realized by pulse frequency modulation (PFM) technique supported with a novel method utilizing extended integration that eliminates the requirement for an additional column ADC. Digital pixel operates with two phases; the first phase is as ordinary PFM in charge domain and the second phase is in time domain, allowing the fine quantization and low quantization noise. A 32×32 prototype has been manufactured and tested. Measured peak SNR at half well fill is 71dB with significant SNR improvement for low illuminated pixels due to extremely low quantization noise. 32×32 ROIC dissipates only 1.1mW and the figure of merit for power dissipation is measured to be 465 fJ/LSB, compared to 930 fJ/LSB and 1470 fJ/LSB of the state of the art.

Design of large dynamic range, low‐power, high‐precision ROIC for quantum dot infrared photo‐detector

Hybrid infrared (IR) focal plane arrays consist of an array of IR photo-detectors, bump-bonded to a silicon CMOS readout integrated circuit (ROIC) chip. Design and optimisation of ROIC for quantum dot IR detectors is a multidimensional problem. The major design challenge is to select appropriate readout circuit topology to meet the large dynamic range requirement of quantum dot IR photo-detectors within the area dictated by the matched pixel size. Proposed is an efficient design optimisation for ROIC. The optimisation is based on a proposed decision matrix, which leads to a decision merit for ROIC design. Four main specifications, i.e. charge handling capacity, noise, power dissipation and detector bias voltage variations, have been considered. Various architectures have been compared using circuit design, simulation and implementation. The targeted ROIC specifications for a test chip containing a 4 × 4 array are: 5 Mē charge handling capacity, 30 × 30 µm maximum pixel size, snapshot mode of operation, variable integration time, 5 megapixels/s (Mpps) readout rate and readout noise of 600ē at ambient temperature. Also presented is a design with 5 Mē charge handling capacity, which has not been reported for 180 nm CMOS process earlier.

Feedforward Effect in Standard CMOS Pinned Photodiodes

The charge handling capacity or the full well of the photodiodes used in CMOS image sensors is a very important characteristic because it affects the saturation level and the dynamic range of the image sensor. The scaling of the pixel size to increase the spatial resolution is also reducing the barrier separating the photon detection and the collection node in a standard pinned photodiode (PPD). The barrier reduction and the thermionic emission of the electrons allow some of the charges from the photodiode well to feed into the collection node, resulting in a feedforward voltage. In conventional readout of the pixels, this feedforward voltage is neglected and lost when the collection node is reset. The barrier height of the transfer gate (TG) determines the quantity of electrons held back in the photodiode well. Thus, the knowledge of this barrier height is very important in determining the true charge handling capacity of the photodiode potential well. Experiments with standard PPDs showed that a barrier height of around 0.5 V is needed to hold the electrons in the photodiode potential well. This is analogous to the barrier potential for charge-coupled devices reported in the literature. Furthermore, the barrier height dependence on the charge storing time in the photodiode well and the structural dimensions of the TG and photodiode length are also explored in this paper.

Characterization of a pnCCD for applications with synchrotron radiation

In this work we study the response of a pnCCD by means of X-ray spectroscopy in the energy range between 6keV and 20keV and by Laue diffraction techniques. The analyses include measurements of characteristic detector parameters like energy resolution, count rate capability and effects of different gain settings. The limit of a single photon counting operation in white beam X-ray diffraction experiments is discussed with regard to the occurrence of pile-up events, for which the energy information about individual photons is lost. In case of monochromatic illumination the pnCCD can be used as a fast conventional CCD with a charge handling capacity (CHC) of about 300,000 electrons per pixel. If the CHC is exceeded, any surplus charge will spill to neighboring pixels perpendicular to the transfer direction due to electrostatic repulsion. The possibilities of increasing the number of storable electrons are investigated for different voltage settings by exposing a single pixel with X-rays generated by a microfocus X-ray source. The pixel binning mode is tested as an alternative approach that enables a pnCCD operation with significantly shorter readout times.

10.1007/s11180-008-2005-y

A new design is described of silicon readout IC for 2D long-wavelength hybrid IR focal-plane arrays. Its essential feature is that the input array is made up of 2 × 2 subarrays of cells. This provides an almost tenfold increase in charge-handling capacity, a major parameter of the readout ICs considered. The design also includes an adaptive digital preprocessing unit in on-chip form.

Current Input Extended Counting ADC With Wide Dynamic Range for LWIR FPAs

A readout circuit incorporating a pixel level analog-to-digital converter (ADC) is studied for 2-D long wavelength infrared focal plane arrays (LWIR FPAs). The charge handling capacity of the unit cell circuit is improved by using the current input incremental ADC. The proposed pixel level ADC is based on an extended counting ADC but is composed of two oversampling conversions. The readout circuit has been fabricated using a 0.35 mum 2-poly 4-metal CMOS process for a 128 times 128 LWIR HgCdTe array with a pixel size of 50 mum times 50 mum. The peak signal-to-noise ratio (S/N) and dynamic range (DR) were measured to be 85.8 dB and 99.9 dB, respectively, with a total power consumption of 50 mW.

Silicon readout ICs for third-generation 2D IR focal-plane arrays operating over the wavelength range 8–12 μm

A new design is described of silicon readout IC for 2D long-wavelength hybrid IR focal-plane arrays. Its essential feature is that the input array is made up of 2 × 2 subarrays of cells. This provides an almost tenfold increase in charge-handling capacity, a major parameter of the readout ICs considered. The design also includes an adaptive digital preprocessing unit in on-chip form.

Random line selected charge accumulation readout structure for random access infrared imager application

A 512×512 monolithic platinum silicide focal plane array with random line selection was proposed. The device was modified from an interline transfer charge couple device configuration by adapting a random line selected charge accumulation structure on a vertical register and four-tap readout structure on a horizontal register to achieve a high fill factor, high charge handling capacity, and high frame rate operation. An on-chip 9-bit decoder was used to select a particular line to transfer charges to their associated vertical charge coupled device (CCD) register. Accompanied with the vertical reset drain circuitry, 1–512 lines can be selected and read out by the vertical CCD registers. The dummy charges on the unselected lines are then transferred to the vertical CCD channel and dumped to the vertical reset drain. In this unique readout structure, a frame rate of upto 240 frames/s can be obtained to select 128×128 of Schottky barrier detectors for 5 MHz clock frequency operation. By changing the selection pattern on a 9-bit decoder, the device can be operated in either interlaced or non-interlaced format, and the charge integration time can be varied which results in variable exposure control. This architecture not only maintains the advantages of CCD structure for its low noise and excellent signal to noise ratio, but also provides readout capability of any portion of the array like MOS structure does.