Characterization Of Through-silicon Vias Research Articles

Fabrication and electrical characterization of partially metallized vias fabricated by inkjet

Through silicon vias (TSVs), acting as vertical interconnections, play an important role in micro-electro-mechanical systems (MEMS) 3D wafer level packaging. Today, taking advantage of nanoparticle inks, inkjet technologies as local filling methods could be used to plate the inside the vias with a conductive material, rather than using a current method, such as chemical vapor deposition or electrolytic growth. This could decrease the processing time, cost and waste material produced. In this work, we have fabricated and demonstrated electrical characterization of TSVs with a top diameter of 85 μm, and partially metallized on their inside walls using silver nanoparticle ink and drop-on-demand inkjet printing. Electrical measurement showed that the resistance of a single via with a void free coverage from top to bottom could be less than 4 Ω, which is still acceptable for MEMS applications.

Analysis of Signal Propagation Through TSVs Within Distilled Water for Liquid-Cooled Microsystems

This paper analyzes the impact of liquid cooling on the electrical characteristics of through-silicon vias (TSVs) using a microfluidic cooling testbed containing TSVs. The microfabrication of TSVs in a silicon micropin-fin heat sink is presented, and the high-frequency characterization of TSVs within a micropin-fin heat sink using distilled water is performed from 10 MHz to 20 GHz. TSV capacitance and conductance are extracted from measurements; TSVs within distilled water have larger capacitance and conductance than TSVs in silicon due to the lossy characteristics of distilled water at high frequencies. A coaxial-like TSV configuration, which consists of multiple ground TSVs surrounding a center signal TSV, is proposed and demonstrated to shield signal TSVs from the coolant.

Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction

Strain measurements are demonstrated for through-silicon vias (TSVs) using synchrotron x-ray diffraction to characterize the effect of copper via dimensions and liner materials. Reduction in strains in the silicon around TSVs is observed for the TSVs with smaller via diameters and the TSVs with a thicker polymer liner. To interpret the measured two-dimensional (2D) TSV strain distribution maps of the three-dimensional (3D) TSV strains, a data averaging method based on the energy dependent x-ray absorption is implemented along with additional considerations from the sample preparation by means of an indirect comparison methodology.

Air-Gap Through-Silicon Vias

This letter reports for the first time the fabrication and characterization of through-silicon vias (TSVs) using air-gap insulators to enable high-performance 3-D integration. To address the challenge in fabricating extremely high-aspect-ratio air gaps, a CMOS-compatible sacrificial technology based on pyrolysis of poly (propylene carbonate) has been developed, upon which air-gap TSVs have been successfully achieved. The measured capacitance density and leakage current density of air-gap TSVs are 1.22 nF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 10 nA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively, about one order and two orders lower in magnitude than TSVs using SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> insulators.

Test Structures for Characterization of Through-Silicon Vias

3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images.

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.