Channel Tunneling Field-effect Transistors Research Articles

GaSb/Si Heterojunction Based Pocket Engineered Vertical Non-Uniform Channel Double Gate TFETs for Low Power Applications

This article compares the performance of two Vertical Non-Uniform Channel Double Gate Tunnel Field Effect Transistors (VNUCDGTFETs), a normal all-Silicon Tunnel Field-Effect Transistor (TFET) having a pocket and another one a Gallium Antimonide/Silicon heterojunction TFET with pocket. GaSb is a III-V narrow energy band gap material, employed in the source area of the TFET structure to decrease the tunneling width and thus to make more number of carriers capable enough to tunnel through the heterojunction. The proposed source pocket heterojunction non uniform channel TFET presents superior performance as compared to the conventional non uniform channel vertical TFET with a pocket, regarding a larger ION/IOFF ratio, a reduced sub-threshold swing, and a smaller threshold voltage at VDS = 0.5 V. Furthermore, the proposed TFET device undergoes a comprehensive analysis of both DC parameters and various analog/RF parameters.

Physics based model development of a double gate reverse T-shaped channel TFET including 1D and 2D band-to-band tunneling components

In this article, a Double gate reverse T-shaped channel tunnel field effect transistor (DG-RT-TFET) is mathematically modeled. The TFET has the potential for exhibiting various types of tunneling mechanisms. The modeled device encompasses both 1D and 2D Band-to-Band (BTBT) tunneling components, with each component developed in the epi-channel and channel, respectively. The study reveals that the 2D BTBT components exhibit greater dominance in the lower gate bias or subthreshold region, while the 1D BTBT becomes more prominent at higher gate bias voltages. By incorporating both models, a more comprehensive understanding of the DG-RT-TFET behavior can be achieved. To ensure the accuracy and reliability of the developed model, all model parameters are calibrated using the TCAD-sentaurus simulator. By comparing the results obtained from the developed model with the simulation results, it is concluded that the developed model for the DG-RT-TFET is suitable for capturing the device behavior and characteristics.

Performance Boost of Si TFETs by Insertion of III–V Dipole Formation Layer: A First Principle Study

Silicon channel tunnel field-effect transistors (TFETs) are known to exhibit low ON-state current due to the wide indirect band gap. In this work, to achieve high ON-state current, we propose a Si TFET with an ultra-thin dipole formation layer (DFL) inserted at the source/channel junction. The inserted DFL forms charge transfer dipoles at the interface, resulting in a staggered band gap. As the consequence, the effective tunnel barrier for electrons is significantly lowered so that ON-state current increases by orders of magnitude. To analyze the characteristics of DFL-inserted Si TFETs, we have solved nonequilibrium Green’s function (NEGF) and Poisson’s equation using density functional theory (DFT) Hamiltonians. We demonstrate that DFL-inserted Si TFETs show boosted performance over conventional TFETs, exhibiting high ON-state current and steep subthreshold swing (SS).

Impactful Study of F-shaped Tunnel FET

In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric field crowding effect at the corners of the source region which reflect in terms of high ON-current (Ion). The Ion of the proposed device is increased up to 10− 4 A/μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.

DC and analog/RF performance analysis of gate extended U-shaped channel tunnel field effect transistor

The DC and Analog/RF performance of Gate Extended-U-shaped channel tunneling field-effect transistors (GE-UTFET) was examined in this study. The performance of the device was investigated through technology computer added design in terms of transconductance (gm), intrinsic capacitances (Cgg, Cgs, and Cgd), cut-off frequency (fT), and gain-bandwidth product (fA). Simulation results show that GE-UTFET has an improved DC characteristic than UTFET. Also, the better RF performance of GE-UTFET than UTFET makes it more suitable for high-frequency application which is attributed to the reduced miller capacitance (Cgd) and enhanced gm.

Heterostructure Ge-Body pTFETs for Analog/RF Applications

This article presents a systematic study on the analog and radio-frequency (RF) performance of type-II staggered heterostructure ${p}$ -channel tunnel field-effect transistors ( ${p}$ TFETs) with Ge (Germanium) channel and different compound semiconductor source. In order to study the figure-of-merits (FOMs) of analog and RF performances, various Ge-channel ${p}$ TFETs are designed with Ge, GaAsP, SiGe, and InAlAs sources. The numerical simulation data show an improvement in the FOMs of analog performance such as drain current ( $I_{ds}$ ), transconductance ( $g_{m}$ ), transconductance-generation-factor ( $g_{m}$ /I $_{ds}$ ), and intrinsic gain ( $g_{m}$ $R_{o}$ ) of the devices with compound semiconductor source compared to Ge-source ${p}$ TFET devices. Similarly, an improvement in the RF FOMs such as gate-to-source ( $\text{C}_{gs}$ ) and gate-to-drain ( $\text{C}_{gd}$ ) capacitances, maximum frequency of oscillation ( $f_{MAX}$ ), and cutoff frequency ( $f_{T}$ ) is observed for the devices with GaAsP, SiGe, and InAlAs source compared to Ge-source ${p}$ TFETs. The simulation results also show that the common-source amplifiers, designed with Ge-heterostructure ${p}$ TFETs, exhibit a significant enhancement in gain and Gain-Bandwidth product of the circuit.

Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique

In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.

Effects of ZrO2/Al2O3 Gate-Stack on the Performance of Planar-Type InGaAs TFET

We investigate the impact of gate-stack engineering using W/ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with the dielectric constant of around 40 on In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As. On the other hand, the reduction of Dit by insertion of ALD 1-5 cycle Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S.Smin) of 55 mV/dec and ION of 0.88 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, and IOFF = 10 pA/μm). Furthermore, the ZrO2/Al2O3 IL gatestack is applied to the optimized In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As quantum well (QW) channel TFETs. The low S.Smin of 50 mV/dec and high ION of 1.2 μA/μm (VG-VOFF = 0.5 V, VD = 0.2 V, IOFF = 10 pA/μm, and CET = 1.1 nm) are demonstrated by combing the present ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate-stack with the optimum In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> As QW channel structure.

Covered Source–Channel Tunnel Field-Effect Transistors With Trench Gate Structures

We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, on/off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on/off current ratio of approximately 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , an on-current of approximately 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on-current of the CSC-TFETs is ~233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.

Influence of impurity concentration in Ge sources on electrical properties of Ge/Si hetero-junction tunneling field-effect transistors

We have experimentally demonstrated that there is the optimum B doping concentration in the Ge source in terms of the electric performance of Ge/Si hetero-junction tunneling field-effect transistors (TFETs). The degradation in subthreshold swing (SS) is observed for TFETs with the source B concentration higher than 1 × 1020 cm−3, which can cause the degeneration in Ge. This source concentration dependence can be explained by the depression of the energy filtering effect due to the degeneracy of the Fermi level (EF). This interpretation is supported by the temperature dependence of SS in the Ge/Si TFETs with different source concentrations. Also, a low SS value of 60.6 mV/dec, an Ion value of 82.3 nA/μm, and a large Ion/Ioff ratio of 6.8 × 106 are obtained for the 1.1% tensile strain channel with the optimized B concentration in the Ge source. It is found that the influence of the source EF on the electrical characteristics of TFETs is more pronounced for the strained-Si channel TFETs with smaller Eg.eff.

TCAD Simulation of Single-Event-Transient Effects in L-Shaped Channel Tunneling Field-Effect Transistors

Tunnel field-effect transistors (TFETs) have promising structures for future ultrascaled devices thanks to their capability in reducing swing threshold and short channel effects. In this paper, Si-based L-shaped channel TFETs (LTFETs) with buried oxide layers subjected to heavy-ion irradiation are scrutinized using Technology Computer-Aided Design simulation for the first time. The effects of linear energy transfer and voltage bias on single-event effects (SEEs) are investigated. Results show that the peak value of drain current in LTFET reaches up to $2.59 \times 10^{-4}$ A at $10 ~\text {MeV}\cdot \text {cm}^{2}$ /mg, which is much higher than the on-state current at $V_{d} = 0.5$ V. Moreover, it indicates that LTFET is more sensitive to SEE than fully depleted silicon-on-insulator MOSFET with back-plane layer. Meanwhile, overall analysis shows that the charge collection process in LTFET device is mainly due to the drift–diffusion mechanism and the bipolar amplification effect can be eliminated. A part of the hole produced by ion strikes will diffuse from the body into the drain region and help reduce the duration of transient. Moreover, by simulating heavy-ion strike in the lateral and vertical channels in LTFETs, the tunneling junction was first confirmed as the most sensitive part of the TFET against heavy-ion impacts, where the highest electric field in the device is found. These findings give a new insight into the SEE in TFETs, which can provide guidelines for the future radiation-hardened applications for TFET-based circuits.

Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET

ABSTRACTAmbipolar conduction in tunnel field-effect transistors (TFETs) has been occurred as an inherent issue due to drain-channel tunneling. It makes TFET less efficient and restricts its application in complementary digital circuits. Therefore, this manuscript reports the application of Gaussian doping profile on nanometer regime silicon channel TFETs to completely eliminate the ambipolarity. For this, Gaussian doping is used in the drain region of conventional gate-drain overlap TFET to control the tunneling of electrons from the valence band of channel to the conduction band of drain. As a result, barrier width at the drain/channel junction increases significantly leading to the suppression of an ambipolar current even when higher doping concentration (1 10 cm ) is considered in the drain region. However, significant improvement in terms of RF figure-of-merits such as cut-off frequency (f ), gain bandwidth product (GBW), and gate-to-drain capacitance (C ) is achieved with Gaussian doped gate on drain overlap TFET as compared to its counterpart TFET.

Impact of source height on the characteristic of U-shaped channel tunnel field-effect transistor

Tunnel field-effect transistor (TFET) is very attractive in replacing a MOSFET, particularly for low-power nanoelectronic circuits. The U-shaped channel TFET (U-TFET) was proposed to improve the drain-source current with a reduced footprint. In this work, the impact of the source height (HS) on the characteristic of the U-shaped channel tunnel field-effect transistor (U-TFET) is investigated by using TCAD simulation. It is found that with a fixed gate height (HG) the drain-source current has a negative correlation with HS. This is because when the gate region is deeper than the source region, the electric field near the corner of the tunneling junction can be enhanced and the tunneling rate is increased. When HS becomes very thin, the drain-source current is limited by the source region volume. The U-TFET with an n+ pocket is also studied and the same trend is observed.

Analog/RF performance of L- and U-shaped channel tunneling field-effect transistors and their application as digital inverters

The inverter performance comparisons of L- and U-shaped channel tunneling field-effect transistors (LTFET and UTFET) are investigated by using Sentaurus TCAD tool. The RF figures of merit for these two TFETs are analyzed in terms of transconductance (gm), output conductance (gds), gate capacitance (Cgg), gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), unit-gain cut-off frequency (fT), the maximum frequency of oscillation (fMAX) and gain bandwidth product (GBW). The simulation results reveal that LTFET and UTFET have the similar DC characteristic due to the identical tunneling process. And the better RF performance LTFET provides due to it has the much smaller Cgd than UTFET. Meanwhile, this work uses mixed device-circuit simulations to predict the performance of inverter circuit implemented with LTFET and UTFET for the first time. And the calculated results demonstrate LTFET is more optimization for inverter circuit design in the novel generation transistors. And all the simulation results in this paper can be used as a reference to choose the characteristic parameters of novel TFETs for inverter applications.

Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

Effects of using asymmetric channel thickness in tunneling field-effect transistors (TFET) are investigated in sub-50 nm channel regime using two-dimensional (2D) simulations. As the thickness of the source side becomes narrower in narrow-source wide-drain (NSWD) TFETs, the threshold voltage (Vth) and the subthreshold swing (SS) decrease due to enhanced gate controllability of the source side. The narrow source thickness can make the band-to-band tunneling (BTBT) distance shorter and induce much higher electric field near the source junction at the on-state condition. In contrast, in a TFET with wide-source narrow-drain (WSND), the SS shows almost constant values and the Vth slightly increases with narrowing thickness of the drain side. In addition, the ambipolar current can rapidly become larger with smaller thickness on the drain side because of the shorter BTBT distance and the higher electric-field at the drain junction. The on-current of the asymmetric channel TFET is lower than that of conventional TFETs due to the volume limitation of the NSWD TFET and high series resistance of the WSND TFET. The on-current is almost determined by the channel thickness of the source side.

Analog/RF performance of four different Tunneling FETs with the recessed channels

In this paper, the performance comparisons of analog and radio frequency (RF) in the four different tunneling field effect transistors (TFETs) with the recessed channels are performed. The L-shaped channel TFET (LTFET), U-shaped channel TFET (UTFET), U-shaped channel with L-shaped gate TFET (LGUTFET) and U-shaped channel with dual sources TFET (DUTFET) are investigated by using Silvaco-Atalas simulation tool. The transconductance (gm), output conductance (gds), gate capacitance (Cgg), cut-off frequency (fT) and gain bandwidth product (GBW) are the parameters by analyzed. Among all the considered devices, the DUTFET has the maximum gm and gds due to the improved on-state current by dual sources, and the LTFET has the minimum Cgg because of the minimum gate-to-drain capacitance (Cgd). Since analog/RF characteristics of a device are proportional to gm and inversely proportional to Cgg, the LTFET and DUTFET have better analog/RF performance compared to the UTFET and LGUTFET. The extracted largest fT is 3.02 GHz in the LTFET and the largest GBW is 1.02 GHz in the DUTFET. The simulation results in this paper can be used as a reference to choose the TFET among these four TFETs for analog/RF applications.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in IOFF of ∼ 9 × 10−16 A/μm, ION of ∼20 μA/μm, ION/IOFF of ∼2 × 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.

Effects of dual-spacer dielectrics on low-power and high-speed performance of sub-10 nm tunneling field-effect transistors

In this paper, we propose and investigate a dual-spacer dielectric structure for realizing a sub-10 nm tunneling field-effect transistors (TFET) with excellent low-power (LP) and switching performance. The effects of the dual-spacer dielectric were assessed by analyzing the direct current (DC) and radio frequency (RF) performance of the GaAs0.5Sb0.5/In0.53Ga0.47As heterojunction-based short channel TFETs. The dual-spacer dielectric that consists of hafnium oxide (HfO2) and silicon dioxide (SiO2) raises an energy-band on drain-side because of the fringe field induced by the high-k spacer dielectric HfO2. The raised energy-band suppresses direct band-to-band tunneling (BBT) through the channel region and drain-induced barrier thinning (DIBT) phenomenon with improvement in the off-state current (Ioff) and subthreshold swing (S). The dual-spacer dielectric also influences total gate capacitance (Cgg) because the HfO2 in the dual-spacer dielectric increases out-fringe capacitance (Cof) in gate-to-drain capacitance (Cgd). Although the proposed TFET has a high Cgd, the optimized TFET with the HfO2 length (Ldual-spacer) of 30 nm achieves a lower intrinsic delay time (τ), a higher cut-off frequency (fT), and a higher maximum oscillation frequency (fmax) owing to higher current performance and smaller gate-to-source capacitance (Cgs).

High Performance of Fin-Shaped Tunnel Field-Effect Transistor SONOS Nonvolatile Memory With All Programming Mechanisms in Single Device

This paper demonstrates a silicon-oxide-nitrideoxide-silicon (SONOS) nonvolatile memory (NVM) with fin-shaped polycrystalline silicon channel tunnel field-effect transistor (TFET). It differs from other memory devices in that its programming mechanisms include Fowler-Nordheim (FN) tunneling, channel hot-electron (CHE) injection, and band-to-band tunneling-induced hot electron (BBHE) in single memory cell. In FN programming, both the ON-state current and the program/erase (P/E) operations are based on quantum tunneling. For FN tunneling, when a V \(_{{{\rm G}}}\) of 17 V is applied for only 1 ms, this device has a large threshold voltage shift ( \(\Delta V_{\mathrm {\mathbf {TH}}}\) ) of 4.7 V. The fin-shaped TFET SONOS (T-SONOS) NVM exhibits superior endurance of 88% after 104 P/E cycles. The memory window remains 65% of its original value after 10 years at a high temperature of 85 °C. On the other hand, the device exhibits better endurance of 74% for CHE programming and BBHE programming after 104 P/E cycles. The memory window retains 81% in CHE programming and 65% in BBHE programming after 10 years. The fin-shaped T-SONOS NVM exhibits high performance that can be achieved in polycrystalline silicon NVM.

Device and Circuit Performance Evaluation of Extended Channel SiGe Double Gate Tunnel FETs

In recent past extensive simulation work on Tunnel Field Effect Transistors (TFETs) has already been done. However this is limited to device performance analysis. Evaluation of circuit performance is a topic that is very little touched. This is due to the non-availability of compact models of TFETs in the commercial simulator. We generate the TFET model by using the model editor in Cadence OrCAD V16.0. In this paper for the first time we perform the circuit analysis of Extended Channel Tunnel Field Effect Transistors (Extended Channel TFETs), we test them over basic digital circuit. Before that we perform device analysis of double gate extended channel TFETs, extended channel has been tried before on SOI TFETs, we try it for the first time on double gate Si1-xGex TFETs. We even look at the effect of introducing Si layer. The performance of this device is compared for different Ge mole fraction and also with MOSFETs.