Thin-film Transistors Channel Research Articles

SC-CNTs: Thin Film Transistors for High-Performance, Low-Power, Flexible Electronics

Single Walled Carbon Nanotubes (SWNTs) have gained a great deal of media attention over the past almost-two decades. From their theoretical usage as the foundational material for space elevators that would take travelers beyond earth’s atmosphere, to an active material that would allow engineers to create nanobots that internally repair or treat the human body, applications for SWNTs are numerous and have resonated within the imagination of scientists and the media alike. Fast forwarding to the modern era, we find that nanotubes still have a great deal of technological promise, some of which parallel those usages that were theoretically conceived many years ago.For over a decade, NanoIntegris Technologies Inc. has been at the forefront of synthesizing high-purity, electronically enriched SWNT’s and, during that time, has found that our materials have proven to transcend from the theoretical to practical-usage realm. With over 1,900 publications citing the usage of NanoIntegris’ high performance materials, we have not only seen the beneficial properties of our materials studied via techniques such as scanning electron microscopy but have also received many positive use-cases for our materials such as being an additive of highly-conductive, electrode (anode/ cathode) slurries of next-generation lithium-ion batteries, to being used as an active for the highly-sensitive detection of COVID antigens.Within my talk, I will display the usage of our high-purity semiconducting (≥99%) single walled carbon nanotubes to make the next generation of high-performance electronics. I will focus upon the usage of our IsoSol-S100 semiconducting solution that served as the spin-coated semiconducting layer within a short channel (<10 µm) thin film transistor with ON/OFF of 104, a device thickness of 400 nm, and a mobility of 39 cm2V-1s-1. I will further discuss the usage of our IsoNanotubes-S 99% solution to serve as the active material within a low-power, wearable Radio Frequency biosensor that covers the GSM spectra, with an operation frequency up to 2.1GHz, and that can serve as both a frequency multiplier and mixer.

P‐12: Improve the Reliability of a‐IGZO TFT through Optimizing the Threshold Voltage and Channel Thickness in AMOLED Hybrid Backplane

In the fabrication of flexible a‐IGZO and LTPS thin film transistor (TFT) hybrid backplane, various threshold voltage (Vth) of the a‐IGZO TFT was achieved in this paper by regulating the O2/Ar ratio during the deposition of a‐IGZO film by sputtering. The results show that the Vth increases with the increase of the O2/Ar ratio, and the reliability tests indicate that in a certain range negative adjustment of Vth can significantly improve the positive bias temperature instability (PBTI) of IGZO TFT, and maintain good electrical uniformity. The increase of the O2/Ar ratio reduces the number of oxygen vacancy (Vo) in the a‐IGZO channel, and thereby Vth is positively shifted, which is confirmed by the TCAD simulation. The Vth value can indicate the Vo concentration in a‐IGZO TFT channel partly, and appropriately higher amount of Vo is beneficial to improve the PBTI, which is attributed to Fermi level (EF) shifting closer to conduction band. Raised EF means less unoccupied trap states, resulting in less carrier trapping under PBTI. Furthermore, the research also explores different a‐IGZO channel thicknesses and finds that when the Vth values are similar, thinner channel layers endow a‐IGZO TFT with improved PBTI. By optimizing the Vth and channel thickness, a‐IGZO TFTs with a channel thickness of 25nm and a Vth value of 0.2V have been prepared in a hybrid backplane. Under positive bias temperature stress for 5 hours, the Vth is positively shifted less than 0.5 V, which could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.

P‐17: Development of Vertical Oxide Channel Thin Film Transistor Based on Hard‐Mask Etching

Avertical oxide semiconductor thin film transistor (VTFT) with channel lengthof 0.4 μm wasdeveloped in our work. This VTFT has a small footprint, which isconducive to achieving higher resolutiom. In this work, we produced a VTFT by usinga hardmask etching process and designed different vertical structures, such asslope, hole, etc. The device achieved an on‐state current of 20.6 μA (normalized with width) and an off‐state current below 1 pA.

Scaling Benefits for Active and Gate Insulator of Vertical Channel Thin-Film Transistors Using Atomic Layer Deposited InGaZnO Channel

Scaling Benefits for Active and Gate Insulator of Vertical Channel Thin-Film Transistors Using Atomic Layer Deposited InGaZnO Channel

Sodium adsorption on nanometer-thick TiO2 channel thin-film transistors for enhanced drain currents

Sodium adsorption on nanometer-thick-TiO2-channel thin-film transistors (TFTs) are examined for enhancing the drain current. In the TFTs, the channel thickness of TiO2 is set as thin as ∼16 nm. The TiO2 film is deposited by atomic layer deposition using plasma excited humified Ar, followed by crystallization into the anatase phase by thermal annealing at 500 °C in air. The gate oxide is a 300 nm thick SiO2 film, which is grown on a highly doped n+ Si substrate. The n+ Si substrate is used as the gate electrode. The drain and source electrodes of Ti are deposited by an electron beam evaporation at room temperature. The TiO2 channel is covered with multiple layers of aluminum silicate and SiO2 films to enhance the Na sorptivity. The multiple films consist of combinations of 1 nm thick SiO2 and 0.16 nm thick aluminum silicate. The channel length and width are 60 and 1000 μm, respectively. The TFT without the Na adsorption exhibits a field effect mobility of ∼0.5 cm2/V s, where the drain current is recorded around 30 μA with a gate voltage of 10 V. With immersion of the TFT in a 10 mM NaCl solution, the drain current is enhanced to the order of mA. The simulation with an equivalent circuit with source and drain resistances suggests that the field effect mobility is enhanced to ∼30 cm2/V s with the adsorption of Na. In this paper, we discuss the operation mechanism of the Na adsorbed TiO2 TFT and its applicability as TFT-based high current switch devices and sensors.

Ferroelectric Controlled Interfacial Effect on the Electronic Properties of PZT Gated IGZO Channel Thin-Film Transistors

Ferroelectric Controlled Interfacial Effect on the Electronic Properties of PZT Gated IGZO Channel Thin-Film Transistors

Bilayer channel structure to improve the stability of solution-processed metal oxide transistors under AC stress

In this work, we report solution-processed bilayer channel thin film transistors (TFTs) based on solution-processed amorphous oxide semiconductors (AOSs) that fulfill both superb electrical performance and device stability against applied alternating current (AC) drain bias stress. Acceptor-like states generation via hot carrier effect (HCE) is a representative device degradation mechanism suggested for AOS-based TFTs when subjected to AC bias stress, featuring threshold voltage (Vth) shift and on-current (Ion) lowering. As excess electric field and accumulated carriers in the AOS channel cause HCE, alleviating carrier accumulation is a key solution for mitigating HCE. Bilayer channel TFTs comprising two different AOSs could work as a countermeasure to overcome HCE since proper energy band alignment of two channels creates a conduction band difference that act as the energy barrier for carriers. In this regard, we employed amorphous indium-gallium-zinc oxide (IGZO) and zinc-tin oxide (ZTO) as bottom and top layer, respectively, for bilayer channel TFT. Designed bilayer channel showed a conduction band difference of 0.18 eV, and fabricated TFT based on this architecture exhibited high mobility over to 5.9 cm2/Vs with slight Vth shift of 0.1 V and Ion lowering of 1.7% for 1000 s against applied AC stress, demonstrating device stability under AC drain bias stress.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Matched printed carbon nanotube complementary metal-oxide-semiconductor (CMOS) devices for flexible circuits

The development of matched carbon nanotube (CNT) complementary metal-oxide-semiconductor (CMOS) devices still remains a challenge for flexible and low-power-dissipation circuits. In this study, we found a reliable technique to achieve matched CNT CMOS thin-film transistors (TFTs) for integrated circuits (IC) with low power consumption. The enhancement-mode p-type CNT TFTs were obtained using the low-work-function Al gate electrodes and ultrathin (10 nm) Al2O3 dielectrics, which exhibit the average field-effect mobility(μ) of 6.5 cm2V−1s−1, subthreshold swing (SS) down to 70–85 mV/dec and on/off ratio up to 106 at the low working voltages between −1.5 V and 0.5 V, as well the outstanding stability and mechanical flexibility after 10,000 cycles of bending. Then, by adjusting the aspect ratios of the TFT channels and selectively dropping the electron-doping inks into p-type CNT TFTs’ channels, matched n-type and p-type CNT TFTs were obtained. Finally, flexible printed CMOS inverters with high noise tolerance (84% of 1/2 VDD), high voltage gain (over 32), and low power consumption (down to 32.9 pW) were successfully constructed, owing to the work style of CMOS circuits and electrically symmetrical n-type and p-type TFTs. Furthermore, good-performance NAND and NOR gates have been demonstrated. This work can effectively resolve the leakage current issue of flexible carbon-based electronics with the ultra-thin dielectrics by optimizing the conductive ink formula and printing technology.

Research Progress of Vertical Channel Thin Film Transistor Device.

Thin film transistors (TFTs) as the core devices for displays, are widely used in various fields including ultra-high-resolution displays, flexible displays, wearable electronic skins and memory devices, especially in terms of sensors. TFTs have now started to move towards miniaturization. Similarly to MOSFETs problem, traditional planar structure TFTs have difficulty in reducing the channel's length sub-1μm under the existing photolithography technology. Vertical channel thin film transistors (V-TFTs) are proposed. It is an effective solution to overcome the miniaturization limit of traditional planar TFTs. So, we summarize the different aspects of VTFTs. Firstly, this paper introduces the structure types, key parameters, and the impact of different preparation methods in devices of V-TFTs. Secondly, an overview of the research progress of V-TFTs' active layer materials in recent years, the characteristics of V-TFTs and their application in examples has proved the enormous application potential of V-TFT in sensing. Finally, in addition to the advantages of V-TFTs, the current technical challenge and their potential solutions are put forward, and the future development trend of this new structure of V-TFTs is proposed.

Functionalized Carbon-Nanotubes-Based Thin-Film Transistor Sensor for Highly Selective Detection of Methane at Room Temperature

Gas sensors based on carbon nanotubes (CNTs) as channel materials have been widely considered as promising candidates for the detection of toxic gas. However, effectively detecting methane (CH4) with CNTs-based sensors remains challenging because nonpolar CH4 molecules find it difficult to directly interact with CNTs. Herein, a functionalized CNTs-based thin-film transistor (TFT) sensor is proposed for the highly effective detection of CH4 at room temperature, where CNTs with high semiconductor purity are used as the main TFT channel. The VO2 and Pd nanoparticles serve as surface-active agents to modify the CNTs, and the surface-modified CNTs-based gas sensor exhibits excellent gas-sensing properties for the detection of CH4. In particular, the Pd@VO2 composite-modified CNTs-based TFT sensor has excellent sensitivity to CH4 in the detection range of 50 to 500 ppm. The detection limit is as low as 50 ppm, and the sensor exhibits excellent selectivity and superior repeatability. The improved gas-sensing properties of the CNTs-based gas sensor is primarily attributed to the modification of the sensitive channel that can promote the electronic interaction between CH4 and gas-sensing materials. This study provides guidance for the development of high-performance CH4 sensors operating at room temperature.

Fully-Solution-Processed Enhancement-Mode Complementary Metal-Oxide-Semiconductor Carbon Nanotube Thin Film Transistors Based on BiI3 -Doped Crosslinked Poly(4-Vinylphenol) Dielectrics for Ultralow-Power Flexible Electronics.

The threshold voltage (Vth ) adjustment of complementary metal-oxide-semiconductor (CMOS) thin film transistors (TFTs) is one of the research hotspotsdue to its key role in energy consumption control of CMOS circuits. Here, ultralow-power flexible CMOS circuits based on well-matched enhancement-mode (E-mode) CMOS single-walled carbon nanotube (SWCNT) TFTs are successfully achieved through tuning the work function of gate electrodes, electron doping, and printing techniques. E-mode P-type CMOS SWCNT TFTs with the full-solution procedure are first obtained through decreasing the work function ofAg gate electrodes directly caused by the deposition of bismuth iodide(BiI3 )-doped solid-state electrolyte dielectrics. After synthetic optimization of dielectric compositions and semiconductor printing process, the flexible printed E-mode SWCNT TFTs show the high Ion /Ioff ratios of ≈106 , small subthreshold swing (SS) of 70-85mV dec-1 ,lowoperating voltages of ≈0.5 to -1.5V, good stabilityand excellent mechanical flexibility during 10000 bending cycles. E-mode N-type SWCNT TFTs are then selectively achieved via printing the polarity conversion ink (2-Amino-2-methyl-1-propanol (AMP) aselectron dopingagent) in P- type TFT channels. Last, printed SWCNT CMOS invertersare successfully constructed with full rail-to-rail output characteristics and the record unit static power consumption of 6.75 fW µm-1 at VDD of 0.2V.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In–Ga–Zn–O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In–Ga–Zn–O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec−1), and high current drivability (13.6 μA μm−1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm−1 for 104 s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Undoped p-type ZnTe thin film and thin film transistor channel performance

Undoped p-type ZnTe thin film and thin film transistor channel performance

Bilayer Metal Oxide Channel Thin Film Transistor With Flat Interface Based on Smooth Transparent Nanopaper Substrate

With the rapid development of electronic devices, a lot of electronic waste is generated yearly. They posed sereve environmental concerns. Integrating sustainable materials into electronic devices is one of promising solutions to achieve the balance between technological development and ecological protection. Cellulose nanopaper has emerged as a hot sustainable material for thin film transistors (TFT) in the flexible display. However, the performance of nanopaper TFT is generally poor. In this study, a transparent nanopaper with a root-mean-square surface roughness of 3.49 nm is prepared by spin coating cellulose nanofibrils on glass and applied as a substrate for metal oxide TFTs. Bilayer channel (IGZO/Al <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> ) TFTs with bottom gate structure are then deposited on transparent nanopaper by physical vapor deposition at room temperature. Consequently, the as-prepared nanopaper TFT not only exhibits a saturation mobility of as high as 21.98 cm2/(V·s), an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text {on}}/\text{I}_{\text {off}}$ </tex-math></inline-formula> ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5.07}\times {10} ^{{6}}$ </tex-math></inline-formula> , and a subthreshold swing of 0.75 V/dec, but shows good bias stability. This work brings a step closer to green, sustainable, and inexpensive transparent paper electronics.

Process Development of Amorphous Indium Tin Gallium Oxide (ITGO) Thin Film Transistors

The invention of portable electronic devices had a huge impact on the growing interest in flat panel displays. Since the first report in 2004 on amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs), many companies have become interested in this material. The main advantage of a-IGZO over conventional amorphous silicon TFTs is its steep subthreshold, low off state current, and high channel mobility. However, the demand for larger displays with higher resolution and refresh rates is driving the demand for TFTs with higher performance, while avoiding the cost and complexity associated with low temperature polycrystalline silicon. There is an increased focus on alternative amorphous oxide semiconductors for use as TFT channel materials, due to the success of a-IGZO.The focus of this study is an investigation on Indium-Tin-Gallium-Oxide (ITGO) TFTs. Unpassivated bottom-gate devices were fabricated with a 30nm a-ITGO film, sputter deposited with 1% and 10% oxygen gas ambient, followed by a 2 hour anneal at 300oC in oxygen. Devices fabricated with PO2 = 1% resulted in a highly conductive channel. Devices with PO2 = 10% displayed semiconducting behavior and a shallow subthreshold. This trend held for all device dimensions tested; lengths of 24µm, 12µm, and 6µm with a width of 24µm. Compared to a-IGZO devices with a length of 4µm, ITGO devices with a length of 12µm exhibit an equivalent current drive, implying a 3 to 4 times improvement in mobility.Following aging in room ambient for multiple days, a-ITGO devices displayed improved yet left-shifted transfer characteristics. In unpassivated a-IGZO devices, similar behavior can also be observed and is attributed to an inhomogeneous trap distribution across the channel. As the exposed channel reacts with room air, oxygen vacancies are filled resulting in a more homogeneous trap distribution. A radial variation of device performance from the center of the wafer to the edge was also observed. When measuring devices towards the edge of the wafer a considerable left shift in transfer characteristics was observed. This variation in device performance is believed to be attributed to non-uniformities in the as deposited ITGO film and will be related to material optical parameters. Figure 1

(Invited, Digital Presentation) Oxide TFTs Based on Semiconductors and Semimetals

Oxide semiconductors have opened a new era for large-area, flexible and transparent applications. Despite the progresses, a bottleneck issue of oxide thin-film transistors (TFTs) is the instability either under bias stress or when used as a current source. Furthermore, the carrier mobility and current driving capability need to be improved for high-spec displays. It is still hugely challenging to overcome both issues using the conventional device structure and oxide semiconductor materials.Here, we review our recent work on novel oxide TFTs that show a few desirable properties. Rather than using an ohmic metal contact as the source electrode, a high work-function Schottky source contact enables depletion around the TFT source region, which results in intrinsic immunity to the negative bias illumination stress, no obvious short channel effect, and superb current saturation over a wide range of drain voltage1. The flat saturation current gives rise to an extremely high voltage gain reaching 23,000, which is, to the best of our knowledge, the highest gain ever achieved by a solid-state transistor to date. The threshold voltage is also found to remain stable under different drain voltages, in contrast to standard TFTs, which may be useful in larger-area displays where the drain voltages of the drive TFTs can differ2. Furthermore, the depletion provided by the Schottky source electrode allows utilizing semi-metal ITO to replace IGZO as the TFT channel layer, which significantly enhances the carrier mobility and current driving capability. Other related work may also be discussed in the talk including oxide Schottky diodes operating beyond 10 GHz3, oxide TFTs operating beyond 1 GHz4, significantly enhanced carrier mobility by self-assembled monolayer treatment5,6, and CMOS-like oxide-based logic circuits7,8. References Extremely high-gain source-gated transistors, J Zhang, J Wilson, G Auton, Y Wang, M Xu, Q Xin, A Song, Proceedings of the National Academy of Sciences 116 (11), 4843-4848 (2019)Comparative Study of Short-Channel Effects Between Source-Gated Transistors and Standard Thin-Film Transistors, Zhenze Wang, Li Luo, Yiming Wang, Jiawei Zhang, and Aimin Song, IEEE Transactions on Electron Devices, 69(2), 561 - 566 (2022).Flexible indium–gallium–zinc–oxide Schottky diode operating beyond 2.45 GHz, J Zhang, Y Li, B Zhang, H Wang, Q Xin, A Song, Nature communications 6 (1), 1-7 (2015).Amorphous-InGaZnO thin-film transistors operating beyond 1 GHz achieved by optimizing the channel and gate dimensions, Y Wang, J Yang, H Wang, J Zhang, H Li, G Zhu, Y Shi, Y Li, Q Wang, Qian Xin, Zhongchao Fan, Fuhua Yang, Aimin Song, IEEE Transactions on Electron Devices 65 (4), 1377-1382 (2018).Significant Performance Improvement of Oxide Thin‐Film Transistors by a Self‐Assembled Monolayer Treatment, W Cai, J Zhang, J Wilson, J Brownless, S Park, L Majewski, A Song, Advanced Electronic Materials 6 (5), 1901421 (2020).Significant performance enhancement of very thin InGaZnO thin-film transistors by a self-assembled monolayer treatment, W Cai, J Wilson, J Zhang, J Brownless, X Zhang, LA Majewski, A Song, ACS Applied Electronic Materials 2 (1), 301-308 (2020).Complementary integrated circuits based on p-type SnO and n-type IGZO thin-film transistors, Y Li, J Yang, Y Wang, P Ma, Y Yuan, J Zhang, Z Lin, L Zhou, Q Xin, Aimin Song, IEEE Electron Device Letters 39 (2), 208-211 (2017).Thin Film Sequential Circuits: Flip-Flops and a Counter Based on p-SnO and n-InGaZnO, Y Yuan, J Yang, Y Wang, Z Hu, L Zhou, Q Xin, A Song, IEEE Electron Device Letters 42 (1), 62-65 (2020).

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel Thin-film-transistor (TFT) TFT materials such as ZnO, InGaZnO, AMO-CNT, and organic materials dramatically improved the achieved and projected TFT performance. The low field mobility of oxide materials has reached values comparable to those for short-channel Si CMOS. The effects related to electron inertia and electron density oscillations in field effect transistors channels (FETs) diminish the role of the low field mobility as a figure of merit in short channel devices making the performance gap between TFTs and Si CMOS smaller enabling high frequency TFT applications even reaching sub-THz and THz frequencies (for the operating regimes using the rectification of the plasma oscillations. We report on an improved compact model based on the RPI TFT model [1] and using the Unified Charge Control Model (UCCM). [2, 3] This model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. It also accommodates the inclusion of the parasitics related to the gate impedance. These new features allowed us to obtain an excellent agreement with the measured I-V/C-V characteristics for both long and short n-channel and p-channel TFTs. The application of this new TFT model to the analysis of the TFT response requires accounting for non-local potential distribution in the device channel. This is achieved by using a multi-segment nonlinear transmission line model of the TFT channel reproducing the approach that has been previously used for the THz SPICE/ADS Si CMOS model implementation. As a possible application example, we simulated a TFT complementary inverter. Our simulations showed that using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT. These results show that the TFT RFID and other applications could be extended into the THz range of frequencies.

Contact resistance in sub-micron and nanoscale organic thin-film transistors

Two improved methods for evaluating contact resistance in organic thin-film transistors (TFTs) are presented. These methods can be applied to TFTs with any arbitrary geometry and are also suitable for retroactive analysis of current-voltage characteristics. The first method is based on the analysis of the differential conductance of TFTs and in separating the conductivity contributions from the contacts and the channel. This method provides accurate results when the contact resistance is approximately 0.1–10 times the channel resistance. The second method is especially applicable to nanoscale and short channel length TFTs. The minimum value of differential on-resistance as a function of drain bias is used to separate the contributions of the channel and contact resistances at various drain voltages. This method is accurate when the contact resistance is approximately 0.3–10 times the channel resistance, as verified by simulations. It works even when there is no distinct saturation in current-voltage characteristics with increasing drain voltage. Both methods have been applied to experimental data from organic TFTs with channel lengths in the range 10 nm to 5 μm. • Two novel methods of extracting contact resistance in OTFTs are introduced. • Contact resistance of various channel lengths OTFTs are extracted and analyzed. • Effects of contact resistance in short channel pentacene TFTs are discussed. • New design of ultra-short channel TFTs is proposed to improve carrier injection.

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel materials such as ZnO, InGaZnO, AMO-CNT, and organic materials and improved fabrication processes dramatically enhanced the achieved and projected thin film transistor (TFT) performance. The effective field-effect mobility of metal oxide TFT materials has reached values comparable to those for short-channel Si CMOS. We report on an improved compact model based on the RPI TFT model, the unified charge control model (UCCM), and the multi-segment TFT compact model. This improved model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. The application of this new TFT model to the analysis of the TFT response showed that a TFT complementary inverter using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT.