Channel Thermal Noise Research Articles

A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology

This brief presents a low-voltage and low-noise ring voltage-controlled oscillator (VCO) where the phase noise performance is improved by reducing the total channel thermal noise injected into the output node of the VCO during the transition period of the output voltage swing. Implemented in a 65-nm CMOS technology, the proposed ring VCO operates from 485.7 to 1011.6 MHz. At 645 MHz, the measured phase noise is $-$ 110.8 dBc/Hz at an offset of 1 MHz while dissipating 10 mW from a 1-V supply.

Impact of impedance-dependent receiver gain on the extracted channel thermal noise in sub-100 nm MOSFETs

To continue the pursuit of Moore’s law, process variations become a very crucial aspect in fabrications, characterization, and modeling for devices with feature size in the sub-100 nm region. To characterize these process variations, measurements are conducted over hundreds or thousands of transistors, and the experimental uncertainties due to the instruments are assumed to be smaller than that of the device itself, and therefore often be overlooked. This assumption might be true for I–V, C–V, or scattering parameter measurements, but this is not the case for high-frequency noise characterization. This paper presents, for the first time, evidence that the instrument can easily contribute 10–17% uncertainties in the measured power spectral densities (PSDs) of the channel thermal noise in 90 nm MOSFETs.

MOSFET Drain Current Noise Modeling With Effective Gate Overdrive and Junction Noise

In this letter, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source-bulk junction and the drain-bulk junction is presented. A unified analytical expression is derived to ensure excellent continuity with smooth transition of drain current noise from weak- to strong-inversion regimes, including the moderate-inversion region. Excellent agreement between simulated and extracted noise data has shown that the proposed model is accurate over different dimensions and operating conditions.

Equivalent Sheet Resistance of Intrinsic Noise in Sub-100-nm MOSFETs

This paper presents the equivalent sheet resistance for the intrinsic channel thermal noise of sub-100-nm MOSFETs for the first time. This newly defined noise sheet resistance is particularly helpful when comparing the noise performance of devices in different technology nodes for low-noise applications. Experimental results for devices in 130-, 90-, and 65-nm CMOS technology nodes are demonstrated. Strategies for the development of future low-noise technologies are suggested.

A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS

In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities have been compared to the channel thermal noise directly extracted from noise measurements on devices fabricated using GLOBALFOUNDRIES’ 0.13 μm RFCMOS technology. The comparison has been done across different channel length, finger width and number of finger for different frequencies, gate biases and drain biases. Excellent agreement between simulated and extracted noise data has shown that the proposed model is scalable over different dimensions and operating conditions. The proposed model is simple and can be easily implemented in a circuit simulation environment.

Physical noise model of a uniformly doped nanoscale FinFET photodetector

The noise mechanisms of a uniformly doped nanoscale FinFET photodetector including quantum mechanical effects is investigated theoretically. A numerical model has been developed for computation of different noise components in nanoscale FinFET. The drain current channel thermal noise under illuminated conditions is calculated. The noise parameters of the nanoscale FinFET equivalent circuit are strongly influenced by the incident optical signal and the quantum mechanical effects are found to play a major role in determining the overall noise performance of the device. It also reveals that the operating frequency can be adjusted suitably to make the noise behavior independent of the incident optical power. Other noise components such as Shot noise, thermal noise and diffusion noise have been calculated for the two port FinFET photodetector. Signal-to-noise ratio (SNR), Bit error rate (BER) and noise equivalent power (NEP) has also been calculated.

Wide-tuning-range, low-phase-noise quadrature ring oscillator exploiting a novel noise canceling technique

This paper presents a novel noise-canceling technique, which is used to improve the phase noise of a two-stage quadrature ring oscillator. The thermal noise canceling circuitry is used to cancel the channel thermal noise of the output transistors in each stage of the oscillator. Simulations using TSMC 0.13μm CMOS technology show a wide frequency tuning range of 315MHz to 6.64GHz and −97.5dBc/Hz at 1MHz offset from 4.7GHz for changing supply from 0.5V to 1.6V. The power consumption is obtained to be 14.8mW. The proposed oscillator can be used in applications such as ultra-wideband systems, and multiband and multimode receivers.

Investigation of Thermal Noise Factor in Nanoscale MOSFETs

In this paper, we investigate the channel thermal noise in nanoscale MOSFETs. Simple analytical model of thermal noise factor in nanoscale MOSFETs is presented and it is verified with accurately measured noise data. The noise factor is expressed in terms of the channel conductance and the electric field in the gradual channel region. The proposed noise model can predict the channel thermal noise behavior in all operating bias regions from the long-channel to nanoscale MOSFETs. From the measurement results, we observed that the thermal noise model for the long-channel MOSFETs does not always underestimate the short-channel thermal noise.

High frequency channel noise measurement and characterization in deep submicron MOSFETs

We evaluate and compare several closed form expressions of channel thermal noise used in circuits with MOSFET devices operating at high frequencies. To verify and compare these models, NMOS devices with channel widths of 120 μm (20 μm * 6 fingers) and channel lengths of 0.18, 0.36, and 0.54 μm were tested. A comparison of extracted and calculated noise data indicates that a model based on drain and overdrive voltages of short channel devices operating at RF frequencies provides the best match between extracted and calculated results for the channel thermal noise over a frequency range of 3 to 6 GHz and a gate overdrive voltage range of 0.2 to 1.2 V.

A Scalable RFCMOS Noise Model

This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time.

Accurate Extraction of Excess Channel Thermal Noise Coefficient in Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model 4

In this paper, the channel thermal noise coefficient of Berkeley short-channel insulated gate field-effect transistor (IGFET) model 4 (BSIM4) is accurately extracted. To extract the noise coefficient of BSIM4, accurate channel thermal noise model was derived, which takes into account velocity saturation, channel length modulation, and carrier heating effects. Simplified short channel thermal noise model becomes a similar form with BSIM's channel thermal noise model which is based on the long-channel theory. From this result we presented the methodology for extraction of the channel thermal noise coefficient. We show the extracted noise coefficient of nanoscale RF metal–oxide–semiconductor field-effect transistor (MOSFET) with Leff = 21 nm.

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65nm and 130nm CMOS technologies, respectively.

Modeling short-channel effects in channel thermal noise and induced-gate noise in MOSFETs in the NQS regime

Analytical expressions for channel thermal noise and induced-gate noise considering mobility degradation and carrier heating in the non-quasi-static regime are presented. At a given frequency, as a function of channel electric field, channel thermal noise current increases for pure carrier heating and decreases for pure mobility degradation. With both effects present, the increase in noise is much slower and under quasi-static approximation, based on the model used, the two effects cancel out. Induced-gate current noise, on the other hand, increases when both effects are present. Individual presence of either of the two short-channel effects produces similar but slower increase. A physical explanation for the above behavior is presented. An elemental analysis for long-channel devices reveals that, under device saturation, thermal voltage fluctuations precisely at a distance (5/9)L eff from the source, do NOT produce any induced-gate current noise.

On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale Metal–Oixde–Semiconductor Field Effect Transistors

The physical origin of the channel thermal noise in nanoscale RF metal–oxide–semiconductor field effect transistors (MOSFETs) is characterized based on an analytical noise model, which takes into account velocity saturation, channel length modulation, and carrier heating effect. These short channel effects increase the channel thermal noise compared with predicted noise from long-channel theory. Among the three effects, the channel length modulation is found to be the most important short channel effect on the channel thermal noise modeling. In addition, spatial distribution of the channel thermal noise is analyzed by using impedance field method. From this analysis, it is identified that the channel thermal noise is dominated by source side noise contributions.

Physical Model of Noise Mechanisms in SOI and Bulk-Silicon MOSFETs for RF Applications

The noise mechanisms at high frequencies in MOSFETs are analyzed and an analytical model is presented for devices operating at gigahertz frequencies. The proposed model is applied to floating body silicon-on-insulator (SOI) as well as bulk-silicon MOS transistors and experimentally verified. The model accounts for the mechanisms of 1) channel thermal noise; 2) shot-noise due to impact ionization; and 3) substrate back-gate-coupled thermal noise. Compact, closed-form analytical expressions of the noise power spectral density and the minimum noise figure (NF) are presented. At the same technology level, the experimental data and the model show that SOI MOSFETs are able to attain lower NF than bulk-silicon devices by reduction of the back-gate transconductance. However, the higher drain electric field in the SOI, and the parasitic bipolar action and floating body enhance impact-ionization-associated shot-noise, which becomes the limiting noise mechanism at drain voltages higher than the drain onset voltage of ldquokinkrdquo effect. A correlation between the onset voltage and the DC electrical characteristics is shown.

Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors

Classical active transmission-line analysis of channel thermal noise and induced-gate noise in a MOSFET is extended to include non-quasi-static effects. For long-channel MOSFETs this results in simple analytical expressions exhibiting a frequency-squared correction to channel thermal noise, a fourth power in frequency correction to induced-gate noise and a new real part to the correlation coefficient between the two varying linearly with frequency. Using the channel segmentation approach the results are verified using Spice simulations. The expressions can be extended to include the induced substrate current noise and incorporated in compact models.

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-mum SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below -12 dB and -10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of -3.55 dBm. The 872 mum times 872 mum DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.

Analytical Noise Parameter Model of Short-Channel RF MOSFETs

In this paper, a simple and improved noise parameter model of RF MOSFETs is developed and verified. Based on the analytical model of channel thermal noise, closed form expressions for four noise parameters are developed from proposed equivalent small signal circuit. The modeling results show a excellent agreement with the measured data of 0.13㎛ CMOS devices.

An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects

In this work, an analytical channel thermal noise model for short channel MOSFETs is derived. The transfer function of the noise was derived by following the Tsividis’ method. The proposed model takes into account the channel length modulation, velocity saturation, and carrier heating effects in the gradual channel region. Modeling results show good agreements with the measured noise data.

130 and 90 nm CMOS technologies for detector front-end applications

IC designers are moving to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 and 90 nm commercial processes are analyzed to provide an evaluation of the impact of technology scaling on the analog performances of a future generation of front-end chips. The behavior of 1/f and channel thermal noise parameters are studied to assess the effects of gate oxide quality and short-channel phenomena in CMOS processes with different gate oxide thickness and minimum channel length. The experimental analysis is focused on the design of low-power front-end circuits.