Equivalent Sheet Resistance of Intrinsic Noise in Sub-100-nm MOSFETs

Abstract

This paper presents the equivalent sheet resistance for the intrinsic channel thermal noise of sub-100-nm MOSFETs for the first time. This newly defined noise sheet resistance is particularly helpful when comparing the noise performance of devices in different technology nodes for low-noise applications. Experimental results for devices in 130-, 90-, and 65-nm CMOS technology nodes are demonstrated. Strategies for the development of future low-noise technologies are suggested.