Channel MOS Transistors Research Articles

Design and fabrication of nanometer measurement platform for better understanding of silicon mechanical properties

Semiconductor industry is experiencing unprecedented growth, still driven by Moore's law, which is continually delivering devices with improved performance at lower costs. The continuation of this development places the industry in a divergent trade-off between economic attractiveness, technological feasibility, and the need for further performance improvement. Since the mainstream semiconductor technologies are silicon-based, new disruptive innovations are needed to gain additional performance margins. The use of nanowires is the preferred approach for preserving electrostatic control in the MOS transistor channel, and the application of mechanical stress is a booster of carrier mobility. It is in this context that this paper presents the design, fabrication, theoretical modeling, and characterization of a measurement platform to characterize the mechanical tensile stress of extremely narrow Si nanowires as small as 14.2 ± 1.12 nm in width. The proposed measurement platform enables a precise control of uniaxial strain, in terms of both amplitude and location, through the implementation of a stoichiometric Si3N4 pulling strand exerting a high tensile force on silicon nanowires. Reported devices are fabricated using a silicon-on-insulator wafer with fully complementary metal–oxide–semiconductor-compatible processing and top-down approach. It is observed that the mechanical strength of nanostructured Si is size-dependent and increases with miniaturization. Characterization revealed a record tensile strength value of 7.53 ± 0.8% (12.73 ± 1.35 GPa) for the narrowest nanowires fabricated using a top-down approach.

Анализ механизмов деградации подзатворных диэлектриков на основе SiO2 в МОП-транзисторах

Nowadays, the developed mathematical models, describing the degradation mechanism of the gate dielectric, permit to determine the value of the operating time to failure of a device depending on its internal properties and operating conditions. These models significantly reduce the time and material required for performing testing and processing of large amounts of experimental data. In the paper the gate dielectric gates based on SiO in n -and p -channel MOS transistors have been studied. It has been found that under the impact of the electric field the degradation of the gate dielectric with 5.3 nm thickness most likely occurs according to the thermochemical model ( E -model) and in case with 7 nm thickness dielectric- in accordance with the anode hole injection model (1/ E -model). The coefficients have been calculated and the analysis of the mathematical models, permitting to determine the service life gate dielectrics based on SiO with 7 nm thickness in n - and p -channel MOS transistors for different values, of their area, operating voltage and temperature, has been performed. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of manufactured MOS transistors.

Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era

In this paper, a new universal technique based on the unique-size MOS transistors is proposed to resolve the analog circuit design bottlenecks imposed by nowadays modern technology downscaling. The method called here “distributed MOS (DMOS) technique” not only permits utilizing minimum-size transistors for analog circuit design, but also paves the way to emerging new generation of modern circuits and systems. It is proved that employing the proposed technique helps the optimum performance of the circuit to be preserved, regardless of minimum-size MOS transistors’ narrow channel effect and channel length modulation. This capability is anticipated to be logically maintained for even smaller transistors offered by future technology. The threshold and early voltage variations versus the MOS transistor channel width and length are investigated by numerical analysis of the data achieved from TSMC library for 180-nm technology using Cadence software, and the result uncertainty ascribed to them exhibited an excellent agreement with the initially developed extended MOS model. Higher linearity with lower THD is interestingly achieved for the new approach. The excellent conformity among the simulation and post-layout results verified the efficiency of the proposed design technique in practical circumstances.

Aspect ratio of radiation-hardened MOS transistors

The reliability of electronics in the proximity of the ionizing radiation is a key requirement in particular in high energy physics, nuclear power or space applications. One way to improve robustness of MOS transistors operating in such environments is to use enclosed layout techniques. This special layout approach helps to maintain leakage current of MOS transistors at low level even after irradiation, in contrast to a linear layout MOS transistor, where leakage current could increase by orders of magnitude. The issue, arising with enclosed layout transistors, is related to channel modelling, since the MOS transistor gate geometry is no more a simple rectangle. In this work, modelling of equivalent width and length dimensions of the MOS transistor channel under the gate is addressed. For this purpose transistors of four types and two layout versions, fabricated in a standard 180 nm CMOS process, are characterized. The accuracy of available models for equivalent channel dimensions is analysed, along with a new simplified geometrical model developed by the authors. They are further compared to the empirically extracted aspect ratio. The improvement possibilities for the considered models are then identified.

Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects

Distributed nature of an MOS transistor becomes significant in high frequencies, especially in the millimeter wave band. Two types of distributed effects are encountered in an MOS transistor: the distributed effect along the transistor channel, referred as nonquasi static (NQS) effect, and the distributed effect along the gate finger. We denote the former as lateral distributed effect and the later as longitudinal distributed effect (LDE). Lateral distributed effect has been studied in many works and has been considered either accurately or approximately in the available MOS small-signal models. However, LDEs have not accurately been accounted for, except for few works in which an MOS transistor has been analyzed using transmission line approach to derive two-port ${Y}$ parameters of the transistor. Unfortunately, the two-port distributed model is not useful when the transistor is used in common gate, common drain, or cascode configurations. In this paper, we have developed a new three-port distributed model of an MOS transistor to accurately capture the LDEs. Furthermore, the proposed model can be used in conjunction with new Berkeley short-channel IGFET model (BSIM) radio frequency (RF) small-signal models, such as BSIM4.7 and BSIM6. To evaluate the proposed model, we have used Taiwan Semiconductor Manufacturing Company 90 nm RF-CMOS technology parameters. Our results show that LDE is considerably more significant than NQS effect in millimeter wave band, in the case of a short channel MOS transistor with long gate finger. This reveals the importance of LDEs in RF MOS transistor models, especially in millimeter wave band applications.

Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

ABSTRACTConventional planar transistor shows shrinking substrate bias effect at scaled technology. On the other hand, epitaxial delta-doped channel (EδDC) transistor shows substantial amount of substrate bias effect even at 16-nm channel length. This paper unveils the physics behind the substrate bias effect of an n-channel EδDC transistor through Technology Computer Aided Design simulation with analytical justifications. The depletion width for an EδDC transistor very weakly depends upon the applied substrate bias, and with scaling down of channel length, the depletion width insignificantly gets widened. The substrate control over the channel is high so that significant amount of substrate depletion charge terminates on the gate, instead of on the source and the drain. The degradation of threshold voltage roll off and drain-induced barrier lowering coefficient with the increase of substrate bias, is less for the EδDC transistor, compared to that of a conventional halo free transistor. The dependence of the substrate bias sensitivity on the thickness of the low-doped epitaxial layer and concentration of the high-doped layer is explored. The effects of reverse substrate bias on leakage power dissipation and intrinsic delay of EδDC and conventional transistors are discussed.

Low Thermal Budget Microwave Annealing for Nisige Schottky Junction Device

I. Background/ Objectives and Goals As continuously scaling down the devices for logic circuit, higher mobility channel materials have been considered to boost driving current such as Ge or SiGe. However, most high mobility materials have a significantly smaller bandgap as compared to Si, which will result in higher Band-To-Band-Tunneling leakage. As a result, S/D and channel engineering must play leading role for boosting the device performance. We, therefore, propose a NiSiGe/n-Si Schottky Junction formed microwave-annealing for the Si capped SiGe quantum well devices (Si/SixGe1-x/Si,x=0~1). II. Methods Fig. 1 shows Process flow of fabricating NiSiGe/n-Si Schottky diodes. The multi-layer structure of Si/Si0.57Ge0.43/Si was grown by ultra-high vacuum chemical vapor deposition system. The channel composed of a 5nm-thick SiGe with biaxial compressive strain and Si cap was grown at 420~500 and 550 °C, respectively. Isolation film SiO2 was deposited on multi-layer architecture after series surface cleaning. Then, the definition of junction active area was accomplished with lithography and wet-etching. Because of bulk annealing characteristic of microwave, the technique was utilized to form NiSiGe as low leakage Schottky junction ranging from 370 to 470 °C for 150 s in N2 ambient. The un-reacted Ni film was removed, followed by Al deposition as the back contact. The characteristics of microwave-annealed-NiSiGe Schottky junction was investigated with AFM, SEM, TEM, XRD, and electrical analyzer. III. Expected Results The SEM images demonstrated the surface morphologies of NiSiGe layer with various annealing temperatures in Fig.2 NiSiGe agglomeration emerged as forming temperature up to 600 °C by rapid thermal annealing (RTA) which will lead to unstable junction current. Relatively, microwave annealing can suppress the formation of junction defects and prevent the agglomeration due to lower forming temperature. For the purpose of distinguishing the pros and cons between the rapid thermal annealing (RTA) in Fig.3(a) and microwave annealing in Fig.3 (b), I-V characteristics were evaluated to check the electrical performance of Schottky junction. Microwave-annealed Schottky junction exhibited better ION/IOFF ratio about 3×105 formed at 390 °C and more stable off-current characteristic as compared to the one with rapid thermal annealing (RTA). In addition, barrier height and ideality factor of the microwave-annealed Schottky was 0.62 eV and 1.07, respectively. High resolution TEM images showed the polycrystalline structure, good uniformity of the NiSiGe and a distinct interface between NiSiGe and Si in Fig.4. IV. Conclusion Microwave annealing is beneficial in integrating quantum well p-channel MOSFETs with Schottky S/D because of its low temperature feature. We believe our microwave-cooperated quantum well architecture is promising for the high performance logic circuits and enable SiGe or Ge channel devices to be integrated on the Si substrate for the future applications. V. R eferences [1] M. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick, and R. Chau, “High Mobility Si/SiGe Strained Channel MOS Transistors with HfO2/TiN Gate Stack,” IEEE International Electron Devices Meeting, p.28, Dec. 2003. Figure 1

Improvement of Germanium Channel Nmosfet By Using Fluorine Co-Implant Methods

1.Background/ Objectives and Goal Ge has been investigated as a high mobility (both hole and electron) channel material as a substitute for silicon channels in order to boost the device performances. In this paper, we successfully fabricated the Ge nMOSFETs by using fluorine co-implant method. The Ge nMOSFETs by using fluorine co-implant method has good performance with ION/IOFF ratio of ~8.6×103 at VDS = 1V and the subthreshold swing of 382 mV/dec. 2.Methods Fig. 1 illustrates the process steps and structure of our Ge nMOSFETs by using F co-implant methods. We use (100)-oriented p-type Ge wafer with resistivity 0.1~0.6 Ω-cm as the starting material. Firstly, a 400 nm field oxide was deposited on p-type Ge substrates after diluted HF cyclic surface clean. The source/drain regions were defined by photolithography, and subsequently the oxide was etched by BOE. Then a implantation was used to create an n+ source/drain with P and F co-implant at different dose and energy. Following by 100nm SiO2 capping layer, dopant activation with different sequence were accomplished through rapid thermal annealing (RTA) at 600 °C in N2. The split table of dose/energy and RTA sequence was shown in table 1. After defining the active region, a GeO2 (~2 nm) was formed at 520°C for 30 s in pure O2 ambient (~1030 mBar) and then an Al2O3 (5 nm) was covered. 3.ExpectedResults/Conclusion/Contribution Fig. 2 shows the I-V characteristics of co-implant n+-p Ge junction for different annealing sequence, we can observe that the reverse leakage currents of n-Ge contacts decreased. The sequence splits are the P implantation following by annealing at 1 minute and then F implantation following by annealing at 1minute / 2 minutes. It’s obvious that the F could passivate the defect through P implantation by sufficient thermal annealing in the P+F@RTA_1+2min co-implant sample with low reverse leakage current than the P+F@RTA_1+1minsample. Fig. 3 shows the ID-VGS transfer characteristic of the control sample and the P+F@RTA_1+2min co-implant sample of nMOSFETs with W/L =100 μm /10 μm. The measurement voltage were in the linear region at VDS = 0.1 V and the saturation region at VDS = 1 V. We can observe that the co-implant nMOSFET have superior ION current, low IOFF current, ION/IOFF ratio and good subthreshold swing. The ION/IOFF ratio of the co-implant nMOSFET was of ~8.6×103 at VDS = 1V and the subthreshold swing was of 382 mV/dec. The white line cutting is the gate dielectric GeO2 (~2 nm) and Al2O3(5 nm) on top of the Ge substrate. The Ge-nMOSFET and n+-p Ge junction device have been demonstrated by F co-implant methods on p-type Ge substrate. The F implantation can passivate the vacancies in Ge substrate and enhance the overall activated fraction of the dopant in Ge. The shallow junction, low off-state leakage current, and low series resistance could be achieved. Moreover, we also use the best condition to fabricate the Ge n-MOSFET, and superior IONcurrent, low IOFF current, ION/IOFF ratio, good subthreshold swing, and low RSD could be realized. The co-implant methods have great potential for leakage current improvement and shallow junction in the conventional Ge process. REFERENCES [1]M. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar,M. Metz, N. Zelick, and R. Chau, “High Mobility Si/SiGe Strained Channel MOS Transistors with HfO2/TiN Gate Stack,”IEEE International Electron DevicesMeeting,p.28, Dec. 2003 [2]T. Krishnamohan, C. Jungemann, and K. C. Saraswat, “A Novel, Very High Performance, Sub-20 nm Depletion-Mode Double-Gate (DMDG) Si/Si,Ge(l.,jSi Channel PMOSFET,” in IEDM Tech. Dig., 2003, pp. 687-690. Figure 1

Channel Profile Design of $\text{E}\delta $ DC MOSFET for High Intrinsic Gain and Low $V_{T}$ Mismatch

In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel ( $\text{E}\delta $ DC) MOS transistor so that the intrinsic gain ( $A_{v}$ ) is high and the threshold voltage ( $V_{T}$ ) mismatch is low. Analytical study shows that a tradeoff relation exists between low $V_{T}$ mismatch and high $A_{V}$ with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized $\text{E}\delta $ DC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized $\text{E}\delta $ DC transistor with respect to the chosen objectives is clearly explained.

A Unified Channel Thermal Noise Model for Short Channel MOS Transistors

A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.

Simulation of the MOS Transistors Structures Channel Technological Problems

The MOS transistor channel structure depends on a number of technological processes. The main problem includes the channel shortening by applying additional impurity distributions in the source and drain areas, using the ion implantation technological operations (TO). In the process it is important to know and accurately determine the right ion implantation TO technological modes. During the simulation we identified the TO critical modes, distorting or breaking down the channel, of the drain and source area formation. Effects of ion implantation TO modes to the transistor output characteristics was identified.

Hot-carrier reliability and breakdown characteristics of multi-finger RF MOS transistors

Hot-carrier reliability and drain breakdown characteristics of multi-finger short channel MOS transistors are studied in detail. Several abnormal characteristics were observed. With the aid of numerical simulation, we found that the shared drain and source regions for adjacent gate fingers can lead to current crowding and result in the finger number-dependent current-voltage characteristics. In addition, the high current density spots near the drain region would result in the significant hot-carrier induced transconductance degradation as well as remarkable drain breakdown voltage lowering.

Transversal Noise Current: An Excess Noise in CMOS Split-Drain Transistors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> An excess-noise current in CMOS Magnetic Sensitive Field Effect Transistor (MAGFET) split-drain transistors is investigated, and a new noise model is proposed. The model is based on the existence of the transversal noise current that stems from the inversion charge layer in the MOS transistor channel. This excess-noise current, along with the one predicted by the classical MOS transistor, produces the total split-drain noise current. Noise spectral density measurements were carried out to verify the proposed model for split-drain MAGFETs manufactured in 0.8- and 0.35-<formula formulatype="inline"><tex>$\mu\hbox{m}$</tex></formula> CMOS, with an equal geometric aspect ratio of 10 <formula formulatype="inline"><tex>$\mu\hbox{m}$</tex></formula>/10 <formula formulatype="inline"><tex>$\mu \hbox{m}$</tex></formula>. </para>

Tunnel DCIV Extraction of Dopant-Impurity Concentration, Oxide Thickness, and Length in the Channel and Extension Regions of Ultrathin Gate-Oxide MOS Transistors

A methodology is described for extracting, between the source and drain, the spatial variations of surface dopant-impurity concentration and oxide thickness in the channel, drain/extension and source/extension regions using experimental tunnel direct current current-voltage data of the drain, source, and basewell terminal currents versus the gate/base voltage. An example is given using an pMOS transistor with W/L=10 /spl mu/m/0.3 /spl mu/m fabricated by a factory 100-nm technology. Zeroth (constant values) and first-order (linear variation with position) representation formulas are used for the impurity concentration and oxide thickness to fit the experimental data, which also give the electrical lengths of the three regions.

Static and dynamic characteristics of an MOS-controlled high-power integrated thyristor

A theoretical analysis of physical processes in an MOS-controlled high-power integrated thyristor is presented. The design of this device and the effect of diffusion layer parameters on the I–V characteristic in the on state are considered. A rigorous calculation and estimates of the maximal anode current that can be turned off, which depends on the holding current of the thyristor structure shunted by an external MOS transistor, are made. This current is calculated as a function of the effective resistance, which includes the resistance of the MOS transistor channel and that of gate metallization. Simulation of the current decay shows that, as the MOS transistor is switched on, the current, after a delay, sharply (within several fractions of a microsecond) drops by about 90% and then goes on decreasing more smoothly.

Direct experimental verification of shot noise in short channel MOS transistors

Drain noise current was measured at an extended temperature range on n-MOS transistors of various lengths made in a 0.18 urn process. A comparison with theoretical noise models strongly indicates t ...

Quantum size aspects of the piezoresistive effect in ultra thin piezoresistors

Proximal probe sensors with an ability to detect extremely small forces (10 −15–10 −18 N) play significant role in scanning probe microscopy applications. The detection of extremely low forces, require producing micromachined cantilevers with as small as possible spring constants, which is considered by the optimization of the sensor design. In the last year many papers describing the fabrication process of producing ultrathin cantilevers (below 100 nm) with integrated piezoresistors for deflection read-out have been published. In the case of such cantilevers the required thickness of piezoresistors is in the range of 50 nm. From a quantum mechanical point of view, an electrical carrier transport confinement in direction perpendicular to the cantilever surface can be expected and in this manner we have to consider the quantum size effect. The goal of the project described in this paper is to calculate and determine the piezoresistive coefficients in p type Si thin (under 50 nm) piezoresistors taking into account the quantum size effect and to compare them with the corresponding coefficients for bulk material. The calculation of the band structure will use the mathematical apparatus of an exact analytical diagonalization six-band k· p model, modified with the envelope function approximation. The behaviour of the thin piezoresistors employed as integrated deflection read-out will be also discussed. Moreover, critical issues in the realization of piezoresistors formed by MOS transistor channel will be presented.

Hybrid Model of Thermostabilization of the Drain Current in n ‐Channel MOS Transistors

A hybrid model, which makes it possible to calculate the influence of the drain voltage and the temperature on the mobility of electrons in the n‐channel of silicon MOS transistors with a high‐alloy substrate in the linear regime of their operation on the basis of a combination of analytical approximations and modeling of electron transfer by the Monte Carlo method, has been proposed.

Comments on "Inversion charge modeling"

For original paper see H.K. Gummel and K. Singhal, ibid., vol.48, p.1585-93 (2001). In the original paper, an implicit relationship for the inversion charge density in the channel of MOS transistors is presented. As an application, the deduction of a compact MOS transistor model is outlined. This correspondence compares some results of this paper with previous relevant publications.

New fabrication technique for nano-MOS transistors with W=25 nm and L=25 nm using only conventional optical lithography

Abstract With regard to the International Technology Roadmap for Semiconductors, a minimum MOS transistor channel length of 20–22 nm is predicted. Although the resolution of optical lithography continually increases, to date there exists no known and proven solutions for structure sizes below 100 nm. In this paper a new method for fabrication of extremely small MOS transistors down to W =25 nm and L =25 nm with low demands to the used lithography is presented. The used technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size.