Changes In Interface State Density Research Articles

Effects of addition of chromium and/or nickel oxides on the electrical characteristics of yttrium oxide-doped high-voltage zinc oxide varistors

The effects of Cr2O3 and/or NiO addition to Y2O3-doped Bi-based high-voltage ZnO varistors were investigated, including crystal structure and interface states analysis. Incorporating 0.35 mol% Cr2O3 in Y-doped varistors increased the single-grain varistor voltage VNNGB from 2.6 to 3.3 V and decreased the leakage current density by a factor of 40, from 2 × 10−5 to 5 × 10-7 A/cm2. The nonlinearity index α before and after degradation increased from 21 to 35. 1.2 mol% NiO increased VNNGB to 4 V. Highest varistor voltage was 1500 V for 0.3 mol% NiO. Resistance to electrical degradation improved with optimal amounts of Cr or Ni by reduction of grain boundary oxygen vacancies. Though the donor density was changed prominently by addition of Cr and/or Ni, changes in the barrier height were suppressed by the change in interface state density. As a result, the change in VNNGB was related mainly to the empty interface state under no bias.

Effects of series resistance and interface state on electrical properties of Al/Er2O3/Eu2O3/SiO2/n-Si/Al MOS capacitors

Advances in Metal-Oxide-Semiconductor (MOS) capacitors fabrication and processing techniques have significantly reduced the adverse effects of processing on the disruption of the ideal MOS devices. However, changes in interface state density and series resistance have remained significant issues for the performance of MOS devices. In this paper, the impacts of multi-layers on the electrical interface states and series resistance characteristics of Al/Er2O3/Eu2O3/SiO2/n-Si/Al MOS capacitors is reported, by analyzing Capacitance – Voltage (C – V), conductance (G/ω – V), series resistance, and interface states density. Ideal characteristics have been observed for obtained series resistance (Rs) and interface state density (Dit), and the calculated values of Dit are in order of (1010 eV2Cm−2). The outcomes have demonstrated that the Rs and the Dit are essential factors that influence the electrical characteristics of the MOS capacitors. Furthermore, interfacial layers are the cause of variations in the Rs and Dit.

Effect of Al Doping on the Reliability of ALD HfO2

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10).In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices.The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004).Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007).M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002).B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000).L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002).W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Influence of gridded gate structure on gas sensing behavior of hydrogen

A gridded Pt/SiO2/Si MOS sensor for hydrogen detection has been fabricated on p-type ⟨100⟩ Si wafer having resistivity (1–6 Ω cm). The SiO2 and Platinum (Pt) gate thickness were kept about 10 nm and 35 nm. The performance of Pt gate MOS sensor was evaluated through C-V characteristics (capacitance vs voltage) upon exposure to H2 (250 ppm–4000ppm) at different frequencies (25 kHz and 50 kHz) in a closed chamber at air ambient atmosphere. The capacitance of the sensor decreases with increase in frequency as well as H2 gas concentration. The flat band voltage characteristics have been evaluated at different frequencies and concentrations. It decreases as the frequency and concentration of gas both increases. The maximum flat band voltage change was observed −0.6 V at 25 kHz. The sensor exhibits better sensitivity (∼88%) at low frequency (25 kHz). The high response of sensor is attributed to the side wall diffusion, increase in surface area caused by inner side wall and increase in porosity, increase in fixed surface state density, spill-over mechanism and change in interface state density on exposure of gas along with the formation of dipole layer.

Fabrication and characterization of gridded Pt/SiO2/Si MOS structure for hydrogen and hydrogen sulphide sensing

A gridded gate Pt/SiO2/Si MOS capacitor has been fabricated for detection of Hydrogen (H2) and Hydrogen Sulphide (H2S) gases. The MOS device was fabricated on P-type Si <100> (1–6 Ω cm) wafer with thermal oxide layer of thickness about 100 Å, whereas, Platinum (Pt) gate of ∼350 Å was deposited by thermal evaporation technique. The C–V (capacitance vs voltage) and G–V (conductance vs voltage) measurements have been performed for the evaluation of gas sensing behavior of fabricated MOS capacitor structure in H2 (250–4000 ppm) and H2S (1000–6000 ppm) gases at both room and 120 °C temperatures, in a closed chamber in air atmosphere. It has been observed that the value of capacitance decreases with increase in gas concentration. The fabricated MOS capacitor sensor has shown better sensitivity towards H2 (88.6%) at room temperature (∼25 °C) as compared to (∼45%) at 120 °C. Scanning electron microscopy (SEM) and Atomic force microscopy (AFM) studies have revealed the porous nature of the deposited metal film. The side wall diffusion, spillover of Hydrogen into oxide layer, increase in fixed oxide charge density, increase in surface area caused by gridded structure, the formation of dipole layer and change in interface state density on gas exposure, may be the mechanisms of gas sensing for improved sensitivity of the fabricated MOS device.

Role of hydrogen in Ge∕HfO2∕Al gate stacks subjected to negative bias temperature instability

This work investigates the role of hydrogen and nitrogen in a Ge∕HfO2∕Al gate stack by comparing the negative bias temperature instability (NBTI) characteristics with and without the surface nitridation of Ge surface prior to HfO2 deposition. Flatband voltage shift, change in interface state density, and stress induced leakage current were also monitored as a function of stress time. Virtually unchanged interface state density as a function of NBTI indicates no atomic hydrogen release from the dangling bond sites. However, the low n value in power law dependence of flatband voltage shift suggests diffusion of molecular hydrogen absorbed at the interface.

Effects of Thermal Annealing for Restoration of UV Irradiation Damage during Plasma Etching Processes

During plasma etching processes, UV and vacuum ultraviolet (VUV) photon irradiation generates defects and causes an increase in interface state density between SiO2 and Si. To understand the effects of pulse-time-modulated plasma on reducing damage, defects in a SiO2 film (E' center) after etching processes were measured using the electron spin resonance (ESR) method. We found that the density of the E' center was markedly reduced using C4F8/O2 pulse-time-modulated (TM) plasma etching, as compared with continuous wave (CW) plasma etching. This corresponds to the changes in interface state density using the charge pumping method. Conversely, in both cases, these E' centers were almost eliminated by H2/N2 annealing at 400 °C. Interface state density, however, remained constant even by annealing in both cases, whereas, interface state density when using TM plasma was much smaller than that when using CW plasma. This result suggests that H2/N2 annealing is not sufficient to restore the interface state density between SiO2 and Si. To reduce the increase in interface state density, UV irradiation damage must first be suppressed during plasma etching. Consequently, a combination of TM plasma etching and thermal annealing is very effective for reducing UV irradiation damage to achieve high reliability in metal–insulator–silicon (MIS) devices.

Correlation of electrical and morphological properties of sputtered aluminum nitride films with deposition temperature

Abstract The present work reports on the little explored correlation of electrical properties in conjunction with morphology of RF sputtered aluminum nitride (AlN) films at different substrate temperatures (100 °C –400 °C). Electrical properties, especially insulator charge density ( Q in ) and interface state density ( D it ) were studied by using Al/AlN/Si (MIS) as a test vehicle. X-ray diffraction, FTIR spectroscopy, AFM and SEM techniques were studied for crystal orientation, bond formation, surface roughness and grain size of AlN film, respectively. Relatively highly c -axis (0 0 2) oriented films were found in between 200 °C and 300 °C with FTIR absorption peak at 682 cm −1 . Decrease in Q in from 7.9 × 10 11 cm −2 to 1.0 × 10 11 cm −2 found to be associated with increase in surface roughness and grain size, with temperature. There is no significant change in interface state density with deposition temperature. It is found that better crystallinity results in a good dielectric constant.

Interface properties of N 2O-annealed SiC metal oxide semiconductor devices

Dry-oxidized and N 2O-annealed n-type 6H–SiC metal-oxide-semiconductor capacitors are investigated at room temperature using a high-frequency C– V technique. Lower oxide-charge and interface-state densities are observed in case of dry-oxidized device. Oxide reliability of the capacitors is also investigated under high-field stress. Compared to a dry-oxidized device, smaller change in interface-state density occurs for a nitrided device under high-field stress. On the other hand, positive flat-band shift of nitrided device is found to be larger after the stress, implying that the nitridation creates acceptor-type interface states and oxide traps in the device. In summary, N 2O nitridation improves the SiO 2/n-type 6H–SiC interface and oxide hardness against stress-induced damage.

Limitations of conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics

A systematic study of the uncertainties, sensitivity and limitations of the conductance technique for extracting the interface state density of tunneling dielectrics is presented. The methodology required to extract device parameters and interface state density from conductance and capacitance data is reviewed and analyzed. The effect of uncertainties in device parameters on extracted interface state density was determined using experimental results of thin oxides (1.4 nm and 2.0 nm). Modeling was used to indicate the effects of various device parameters on the sensitivity of conductance to changes in interface state density. The effect of uncertainties in insulator capacitance of equivalently thin dielectrics on uncertainties in extracted interface state density is minimal. The effect of uncertainties in series resistance increases with increasing bias towards accumulation. An increase in the series resistance of the device causes reduced sensitivity to changes in interface state density especially for interface states located nearer the majority band edge; increasing tunneling current causes increased uncertainties and reduced sensitivity to changes in interface state density especially for interface states nearer midgap.

Charge trap generation in LPCVD oxides under high field stressing

The degradation of low pressure chemical vapor deposited (LPCVD) oxides, prepared using silane and tetra ethyl ortho silicate (TEOS) as the source, has been investigated under high field stressing. The LPCVD oxides exhibit enhanced conductivity for the Fowler-Nordheim tunneling current, which is modeled as an effective lowering of potential barrier at the injecting electrode. The charge to breakdown (Q/sub bd/) of LPCVD oxides depends on both the deposition chemistry and post deposition annealing condition. The change in interface-state density (/spl Delta/D/sub it/), flatband voltage (/spl Delta/V/sub fb/), and gate voltage (/spl Delta/|V/sub g/|) during constant current stressing are studied to identify the degradation mechanism. We see a very good correlation between Q/sub bd/ and /spl Delta/|V/sub g/|, indicating that the degradation in LPCVD oxides is dominated by bulk trap generation and subsequent charge trapping. We present a detailed theoretical analysis to substantiate this.