HPC Challenge Research Articles

Combinatorial metaheuristic methods to optimize the scheduling of scientific workflows in green DVFS-enabled edge-cloud computing

A significant challenge in high-performance computing is to ensure the even distribution of applications across computational resources, preventing issues such as resource fragmentation and network congestion. While cloud computing offers advantages, it introduces scheduling delays caused by data transmission. To address this issue, edge computing has emerged as an alternative to traditional cloud systems, aiming to minimize latency. While various methods have been proposed to address this challenge, they often prioritize one aspect at the expense of overall system performance. In this paper, we present a novel algorithm utilizing ant colony optimization to compute a fitness function and prioritize multiple objectives in scheduling. The algorithm effectively determines how to distribute applications between edge and cloud servers to enhance computational efficiency. This entails a delicate balance between scheduling delays and energy consumption in two distinct phases. Initially, the algorithm identifies applications sensitive to delays and ensures their execution on local edge servers. Subsequently, it identifies applications that require intensive computation and migrates them to the cloud layer, where cloud servers can process them. The results demonstrate that this approach reduces delay costs by 21.19% and decreases energy consumption by 13.76%.

Challenges in High-Performance Computing

High-Performance Computing, HPC, has become one of the most active computer science fields. Driven mainly by the need for high processing capabilities required by algorithms from many areas, such as Big Data, Artificial Intelligence, Data Science, and subjects related to chemistry, physics, and biology, the state-of-art algorithms from these fields are notoriously demanding computer resources. Therefore, choosing the right computer system to optimize their performance is paramount. This article presents the main challenges of future supercomputer systems, highlighting the areas that demand the most of HPC servers; the new architectures, including heterogeneous processors composed of artificial intelligence chips, quantum processors, the adoption of HPC on cloud servers; and the challenges of software developers when facing parallelizing applications. We also discuss challenges regarding non-functional requirements, such as energy consumption and resilience.

ABCD Analysis of Industries Using High-Performance Computing

Purpose: High-Performance Computing (HPC) is the technique of increasing the overall processing capacity of the system, and achieving high performance in solving large problems in science, engineering, or business. This research paper investigated the High-Performance Computing industry using exploratory research methodology and a listing of ABCD analysis is done. Along with this, the identification of various applications and grand challenges in HPC and various Software Tools required for industry-specific application areas of HPC is done. Design/Methodology/Approach: Qualitative exploratory research methodology to perform Industry Analysis of High-Performance Computing using ABCD Analysis. This research paper is written with the literature review of High-Performance Computing (HPC) industries and various software tools available to use in those industries. Findings/Results: Finding of this research paper is the identification of various grand challenges in HPC industries like healthcare and medical field, engineering and design, aerospace sector, urban planning, and infrastructure, finance, and business. It also lists different HPC software tools that can be used to solve these challenges, along with the findings of ABCD analysis of HPC industry. Originality/Value: Listing of ABCD Analysis (Advantages, Benefits, Constraints, and Disadvantages) of High-Performance Computing industry. Paper Type: Industry Analysis research paper

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks

While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, and not least, benchmarks and reference implementations towards sustained HPC usage of these devices. As in the early days of GPUs in HPC, for workloads that can reasonably be decoupled into loosely coupled working sets, multi-accelerator support can be achieved by using standard communication interfaces like MPI on the host side. However, for performance and productivity, some applications can profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities here when extending the dataflow characteristics to their communication interfaces.In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA support and three missing benchmarks that particularly characterize or stress inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented for current boards with Intel and Xilinx FPGAs, we established a baseline for multi-FPGA performance. Additionally, for the communication-centric benchmarks, we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched inter-FPGA network that is currently only available for one of the boards. The evaluation with parallel execution on up to 26 FPGA boards makes use of one of the largest academic FPGA installations.

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm 2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.

A power constrained approximate multiplier with a high level of configurability

Approximate computing helps tackle the challenges of future embedded and high-performance computing by using various methodologies. By increasing the volume of computations and limiting the power consumption, approximate computing can address these challenges in various demands. Approximate computing aims to achieve acceptable accuracy, rather than exact and correct results and can be used in error-tolerant applications to reduce hardware resources, delay, and most importantly power consumption. This paper introduces a new approximate multiplier, with a high degree of configurability, for unsigned numbers. It aims to reduce all hardware metrics besides keeping high accuracy. The proposed method offers well-optimized options in a power-accuracy tradeoff compared to the other configurable algorithm instances. In addition, it provides a wide range of options with power saving from 35% to 85% to satisfy most applications with a desirable power budget. Furthermore, the proposed approximate multiplier has been employed in Discrete Cosine Transform (DCT) applications.

O-Star: An Optical Switching Architecture Featuring Mode and Wavelength-Division Multiplexing for On-Chip Many-Core Systems

In this paper, we propose O-Star, a scalable optical switching architecture for on-chip many-core systems, employing hybrid mode and wavelength division multiplexing technology. The O-Star uses the Benes topology as the core switching module to realize non-blocking switching. Besides, we design a wavelength and mode allocation module to enable each processor to transmit data in parallel. To quantitatively analyze the minimum hardware cost required, we establish a mathematical model for the different number of processors. As a proof of concept, a 64-core optical switching architecture featuring 8-port Benes topology, 2-mode, and 4-wavelength channels is simulated with single channel 25 Gbps data rate. The O-Star is flexible to scale, both for the number of supported processors and the switching capacity. O-Star holds promise for realizing large-scale optical switching networks to address the incoming challenges of high-performance computing (HPC) systems and data center networks (DCNs).

In-depth FPGA accelerator performance evaluation with single node benchmarks from the HPC challenge benchmark suite for Intel and Xilinx FPGAs using OpenCL

Emerging high-level tools lead to a reduced development time for applications on FPGA accelerators while still producing high-quality results. This is one reason for the increased adoption of FPGAs in data center applications which emphasizes the need for a benchmark suite to enable the comparison of FPGA architecture, programming tools, runtimes, and libraries.Because of the lack of such a benchmark suite, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. In an in-depth evaluation, we show that the benchmarks allow to quantify the impact of HBM2 memory in comparison to FPGAs with DDR and to analyze differences in the arithmetic units on current FPGA architectures. Power measurements indicate, that not all benchmark implementations can utilize the full potential of the FPGAs in terms of power efficiency. We are continuing to optimize and port the benchmark for new generations of FPGAs and design tools and we encourage active participation to create a valuable tool for the community.

Teaching and learning HPC through serious games

Serious games provide pathways for learners to develop intuition about concepts that are new to them. Such games are especially valuable in an educational context because they engage students in active learning and provide a means for students to develop mental models from their experiences. Furthermore, for short term learning experiences, such as informal, ungraded workshops, they act as ice-breaker activities that help build a sense of community among disparate learners. Collaborative games also spawn peer-to-peer discussion. These student experiences generally lead to deeper questions and discussions that allow instructors to uncover more concepts and clarify misunderstandings, all of which reinforce learning. The authors have created and incorporated role playing games within informal High Performance Computing (HPC) courses to provide students with tangible hands-on experiences with HPC concepts. All of the games are designed so that learners work collaboratively and take on a role associated with an HPC system. Engaging in the role playing highlights the strengths, weaknesses, and challenges of HPC. In this article we describe the games, how they were integrated into HPC courses, both in-person and virtual, and the lessons learned by both students and instructors. Though played with professional and university learners, the games are easily generalized to other cohorts.

Automatic Code Generation for High-performance Discontinuous Galerkin Methods on Modern Architectures

SIMD vectorization has lately become a key challenge in high-performance computing. However, hand-written explicitly vectorized code often poses a threat to the software’s sustainability. In this publication, we solve this sustainability and performance portability issue by enriching the simulation framework dune-pdelab with a code generation approach. The approach is based on the well-known domain-specific language UFL but combines it with loopy, a more powerful intermediate representation for the computational kernel. Given this flexible tool, we present and implement a new class of vectorization strategies for the assembly of Discontinuous Galerkin methods on hexahedral meshes exploiting the finite element’s tensor product structure. The performance-optimal variant from this class is chosen by the code generator through an auto-tuning approach. The implementation is done within the open source PDE software framework Dune and the discretization module dune-pdelab. The strength of the proposed approach is illustrated with performance measurements for DG schemes for a scalar diffusion reaction equation and the Stokes equation. In our measurements, we utilize both the AVX2 and the AVX512 instruction set, achieving 30% to 40% of the machine’s theoretical peak performance for one matrix-free application of the operator.

Mixed-precision iterative refinement using tensor cores on GPUs to accelerate solution of linear systems.

Double-precision floating-point arithmetic (FP64) has been the de facto standard for engineering and scientific simulations for several decades. Problem complexity and the sheer volume of data coming from various instruments and sensors motivate researchers to mix and match various approaches to optimize compute resources, including different levels of floating-point precision. In recent years, machine learning has motivated hardware support for half-precision floating-point arithmetic. A primary challenge in high-performance computing is to leverage reduced-precision and mixed-precision hardware. We show how the FP16/FP32 Tensor Cores on NVIDIA GPUs can be exploited to accelerate the solution of linear systems of equations Ax = b without sacrificing numerical stability. The techniques we employ include multiprecision LU factorization, the preconditioned generalized minimal residual algorithm (GMRES), and scaling and auto-adaptive rounding to avoid overflow. We also show how to efficiently handle systems with multiple right-hand sides. On the NVIDIA Quadro GV100 (Volta) GPU, we achieve a performance increase and 5× better energy efficiency versus the standard FP64 implementation while maintaining an FP64 level of numerical stability.

More bang for your buck: Boosting performance with capped power consumption

Achieving faster performance without increasing power and energy consumption for computing systems is an outstanding challenge. This paper develops a novel resource allocation scheme for memory-bound applications running on High-Performance Computing (HPC) clusters, aiming to improve application performance without breaching peak power constraints and total energy consumption. Our scheme estimates how the number of processor cores and CPU frequency setting affects the application performance. It then uses the estimate to provide additional compute nodes to memory-bound applications if it is profitable to do so. We implement and apply our algorithm to 12 representative benchmarks from the NAS parallel benchmark and HPC Challenge (HPCC) benchmark suites and evaluate it on a representative HPC cluster. Experimental results show that our approach can effectively mitigate memory contention to improve application performance, and it achieves this without significantly increasing the peak power and overall energy consumption. Our approach obtains on average 12.69% performance improvement over the default resource allocation strategy, but uses 7.06% less total power, which translates into 17.77% energy savings.

Large-Scale Simulation of a Layered Cortical Sheet of Spiking Network Model Using a Tile Partitioning Method.

One of the grand challenges for computational neuroscience and high-performance computing is computer simulation of a human-scale whole brain model with spiking neurons and synaptic plasticity using supercomputers. To achieve such a simulation, the target network model must be partitioned onto a number of computational nodes, and the sub-network models are executed in parallel while communicating spike information across different nodes. However, it remains unclear how the target network model should be partitioned for efficient computing on next generation of supercomputers. Specifically, reducing the communication of spike information across compute nodes is essential, because of the relatively slower network performance than processor and memory. From the viewpoint of biological features, the cerebral cortex and cerebellum contain 99% of neurons and synapses and form layered sheet structures. Therefore, an efficient method to split the network should exploit the layered sheet structures. In this study, we indicate that a tile partitioning method leads to efficient communication. To demonstrate it, a simulation software called MONET (Millefeuille-like Organization NEural neTwork simulator) that partitions a network model as described above was developed. The MONET simulator was implemented on the Japanese flagship supercomputer K, which is composed of 82,944 computational nodes. We examined a performance of calculation, communication and memory consumption in the tile partitioning method for a cortical model with realistic anatomical and physiological parameters. The result showed that the tile partitioning method drastically reduced communication data amount by replacing network communication with DRAM access and sharing the communication data with neighboring neurons. We confirmed the scalability and efficiency of the tile partitioning method on up to 63,504 compute nodes of the K computer for the cortical model. In the companion paper by Yamaura et al., the performance for a cerebellar model was examined. These results suggest that the tile partitioning method will have advantage for a human-scale whole-brain simulation on exascale computers.

PerfBound: Conserving Energy with Bounded Overheads in On/Off-Based HPC Interconnects

Energy and power are key challenges in high-performance computing. System energy efficiency must be significantly improved, and this requires greater efficiency in all subcomponents. An important target of optimization is the interconnect, since network links are always on, consuming power even during idle periods. A large number of HPC machines have a primary interconnect based on Ethernet (about 40 percent of TOP500 machines), which, since 2010, has included support for saving power via Energy Efficient Ethernet (EEE). Nevertheless, it is unlikely that HPC interconnects would use these energy saving modes unless the performance overhead is known and small. This paper presents PerfBound, a self-contained technique to manage on/off-based networks such as EEE, minimizing interconnect link energy consumption subject to a bound on the performance degradation. PerfBound does not require changes to the applications and it uses only local information already available at switches and NICs without introducing additional communication messages, and is also compatible with multi-hop networks. PerfBound is evaluated using traces from a production supercomputer. For twelve out of fourteen applications, PerfBound has high energy savings, up to 70 percent for only 1 percent performance degradation. This paper also presents DynamicFastwake, which extends PerfBound to exploit multiple low-power states. DynamicFastwake achieves an energy–delay product 10 percent lower than the original PerfBound technique.

Performance Analysis of a 3D Wireless Massively Parallel Computer

In previous work, the authors presented a 3D hexagonal wireless direct-interconnect network for a massively parallel computer, with a focus on analysing processor utilisation. In this study, we consider the characteristics of such an architecture in terms of link utilisation and power consumption. We have applied a store-and-forward packet-switching algorithm to both our proposed architecture and a traditional wired 5D direct network (the same as IBM’s Blue Gene). Simulations show that for small and medium-size networks the link utility of the proposed architecture is comparable with (and in some cases even better than) traditional 5D networks. This work demonstrates that there is a potential for wireless processing array concepts to address High-Performance Computing (HPC) challenges whilst alleviating some significant physical construction drawbacks of traditional systems.

Briefing: High-performance computing for city-scale modelling and simulations

Smarter cities and infrastructure are essential if the world is to respond effectively to the critical challenges it faces. As of 2008, and for the first time in human history, more than half of the world's population now live in cities. Yet cities increasingly need to be able to do more with less, to provide for the well-being of their citizens in a truly sustainable way. City-scale simulations are becoming a possibility with advancements in the computing hardware and software technologies. Recent advancements in distributed scaling using Apache Spark is exemplified through a case-study on simulating the traffic flow behaviour of London at per-hour time resolution. The case-study on the response of ground and structures in central Tokyo shows the advancements in multigrid techniques and Finite Element simulations. This paper discusses the advancements and challenges in high-performance computing (hardware, algorithms, software, and visualisation techniques) in achieving the possibility of real-time city-scale simulations.

Toward General Software Level Silent Data Corruption Detection for Parallel Applications

Silent data corruption (SDC) poses a great challenge for high-performance computing (HPC) applications as we move to extreme-scale systems. Mechanisms have been proposed that are able to detect SDC in HPC applications by using the peculiarities of the data (more specifically, its “smoothness” in time and space) to make predictions. However, these data-analytic solutions are still far from fully protecting applications to a level comparable with more expensive solutions such as full replication. In this work, we propose partial replication to overcome this limitation. More specifically, we have observed that not all processes of an MPI application experience the same level of data variability at exactly the same time. Thus, we can smartly choose and replicate only those processes for which the lightweight data-analytic detectors would perform poorly. In addition, we propose a new evaluation method based on the probability that a corruption will pass unnoticed by a particular detector (instead of just reporting overall single-bit precision and recall). In our experiments, we use four applications dealing with different explosions. Our results indicate that our new approach can protect the MPI applications analyzed with 7-70 percent less overhead (depending on the application) than that of full duplication with similar detection recall.

Introduction to the Special Issue on High Performance Computing Solutions for Complex Problems

Introduction to the Special Issue on High Performance Computing Solutions for Complex Problems

Task Scheduling Techniques for Asymmetric Multi-Core Systems

As performance and energy efficiency have become the main challenges for next-generation high-performance computing, asymmetric multi-core architectures can provide solutions to tackle these issues. Parallel programming models need to be able to suit the needs of such systems and keep on increasing the application’s portability and efficiency. This paper proposes two task scheduling approaches that target asymmetric systems. These dynamic scheduling policies reduce total execution time either by detecting the longest or the critical path of the dynamic task dependency graph of the application, or by finding the earliest executor of a task. They use dynamic scheduling and information discoverable during execution, fact that makes them implementable and functional without the need of off-line profiling. In our evaluation we compare these scheduling approaches with two existing state-of the art heterogeneous schedulers and we track their improvement over a FIFO baseline scheduler. We show that the heterogeneous schedulers improve the baseline by up to 1.45 $\times$ in a real 8-core asymmetric system and up to 2.1 $\times$ in a simulated 32-core asymmetric chip.

Implementation and evaluation of the HPC challenge benchmark in the XcalableMP PGAS language

To improve productivity for developing parallel applications on high performance computing systems, the XcalableMP PGAS language has been proposed. XcalableMP supports both a typical parallelization under the “global-view memory model” which uses directives and a flexible parallelization under the “local-view memory model” which uses coarray features. The goal of the present paper is to clarify XcalableMP’s productivity and performance. To do so, we implement and evaluate the high performance computing challenge benchmark, namely, EP STREAM Triad, High Performance Linpack, Global fast Fourier transform, and RandomAccess on the K computer using up to 16,384 compute nodes and a generic cluster system using up to 128 compute nodes. We found that we could more easily implement the benchmarks using XcalableMP rather than using MPI. Moreover, most of the performance results using XcalableMP were almost the same as those using MPI.