Chain Adder Research Articles

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.

Design of Manchester Carry Chain Adder using High speed Domino Logic

Dynamic logic circuits are preferred over static logic circuits for their increased speed performance and lower power consumption. However, they are found prone to false evaluation while cascading multiple stages of dynamic logic circuits. To overcome this problem, the domino logic circuits were proposed by researchers. However, they offer reduced noise margins due to increased leakage current and charge sharing problems. In this paper, Manchester Carry Chain Adder design is explored for use with domino logic and comparison of various domino logic topologies intended for improved noise immunity and reduced leakage current against the proposed structure have been carried out. Wide fan-in gates and 8-bit Manchester Carry Chain Adder (MCC) based on various high speed domino logic circuit topologies have been designed using Cadence® using 180nm technology library from TSMC. Design of 8-bit OR gate, using High Speed Domino (HSD) topology consumes 10.8% lower power in comparison with Controlled-Current Comparison-based domino logic (C3D) topology. Furthermore, it is observed that an 8-bit Manchester Carry Chain adder using HSD topology is 5.027 times faster than C3D topology and the leakage power consumption is also reduced.

DESIGN OF RELIABLE AND EFFICIENT MANCHESTER CARRY CHAIN ADDER BASED 8-BIT ALU FOR HIGH SPEED APPLICATIONS

This paper gives a detailed design and implementation of an 8-bit ALU for using Manchester carry chain adder in order to minimize the delay and power. The designed ALU is simulated using cadence virtuoso 45 nm process technology. The obtained results were compared with the existed results and its clearly indicates the proposed 8 bit ALU is more reliable and accurate with the existed architecture ,And also it occupies less area and faster

Optimized Double Domino Manchester Carry Chain Adders in 45 nm Technology

Optimized Double Domino Manchester Carry Chain Adders in 45 nm Technology

English

Addition is the fundamental operation for any VLSI processors or digital signal processing. In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Here domino logic is used for implementation and simulation of 128 bit Carry- look ahead adder based HSPICE Tool. In adder circuits propagation delay is the main drawback. To overcome this drawback the domino circuits can be analysed and compared with 65nm technology is used. The proposed work is based on 256 bit Manchester Carry chain(MCC) adders compared with different CMOS technologies.

New High-Speed Multioutput Carry Look-Ahead Adders

In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.

Process variation aware dual-V th assignment technique for low power nanoscale CMOS design

This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (V th) assignment technique for the design of low power nanoscale CMOS circuits. The proposed technique is based on the Plackett–Burman Design of Experiment method (PB-DOE) in which sensitivity of each transistor to delay variation due to change in its V th is obtained. The various paths in the circuit are categorized into process sensitive and process-insensitive paths. Transistors in the process sensitive paths are assigned a high V th to reduce the leakage power without affecting performance. The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-V th assignment technique. Moreover, it is shown that the proposed algorithm can be easily extended to assign dual gate length circuits to achieve a further 20% reduction in the leakage power. The robustness of the proposed technique against process variations is demonstrated with extensive Monte Carlo Simulations. The versatility of the proposed approach to reduce the leakage power for a general CMOS circuit is demonstrated using a Manchester carry chain adder.

Low power critical voltage transition logic

PurposeTo show new design methodology of low power circuit design (Low Power Critical Voltage Transition Logic – LPCVTL) over the conventional CVTL methodology. The comparison is in terms of speed, area and power consumption.Design/methodology/approachThe new design employs feedback mechanism with a different clocking methodology to overcome high static power dissipation of conventional CVTL design.FindingsLPCVTL has lower power dissipation property as compared to the conventional CVTL design through the observation of the simulated results of an inverter chain and half adder designs. LPCVTL power dissipation is about eight times smaller than the conventional CVTL.Research limitation/implicationsThe desired clock frequency is limited by the output signal response.Originality/valueLPCVTL is an alternative to dynamic digital IC design methodology which has high speed advantage while maintaining low power consumption.

Fast and gate-count efficient arithmetic logic unit

A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders, a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay.

Area-time-power tradeoffs in parallel adders

In this paper, several classes of parallel, synchronous adders are surveyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and Manchester carry chain adders, the square-root time carry skip and carry select adders, the logarithmic time carry lookahead adder and its variations, and the constant time signed-digit and carry-save adders. Most of the research in the last few decades has concentrated on reducing the delay of addition. With the rising popularity of portable computers, however, the emphasis is on both high speed and low power operation. In this paper we adopt a uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion. The relative merits of the different adders are evaluated by performing a detailed transistor-level simulation of the adders using HSPICE. Among the two's complement adders, a variation of the carry lookahead adder, called ELM, was found to have the best power-delay product. Based on the results of our experiments, a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.

A simple and high speed CMOS carry chain adder architecture

A simple and high speed adder architecture is presented in this paper. This adder uses pass transistor pairs to make a fast CMOS carry chain as used by the Manchester carry chain technique. It uses less hardware, and is faster than conventional ripple-carry adders. It is also significantly faster than the sign-select adder recently described by Srinivas et al. for word lengths less than or equal to 8, and is slightly faster than this adder for word lengths greater than 8. The structure, however, is simpler and more regular. This adder is well suited for VLSI implementation, and provides a useful trade-off between speed and complexity.