Ceramic Pin Grid Array Packages Research Articles

SILICON INTERPOSER – A COST EFFECTIVE SOLUTION FOR PROTOTYPE PACKAGING OF MEMS ACCELEROMETER SENSORS AND ASSOCIATED ROIC

Assembly and packaging of accelerometer sensors and associated ROIC into a single compact package in an open tool Ceramic Pin Grid Array (CPGA) package with the help of a silicon interposer was explored as a cost effective solution. A Silicon Interposer was designed, fabricated and assembled in an open-tool 120 pin CPGA package

2维位置灵敏中子探测器读出

The design of readout electronics based on multi-channel charge-sensitive pre-amplifier application specific integrated circuit(ASIC) are introduced，which is to be applied in the two-dimensional position-sensitive thermal neutron detector based on thick gas electron multiplier(THGEM). The ASIC is VA64TA2, a bare chip with 64 channels of charge sensitive preamplifier-shaper circuits and every channel with the function of trigger. These chips are packaged with the ceramic pin grid array package CPGA257, with 257 pints. The readout electronics is controlled by FPGA. The results of single-channel linear performance test and electronics noise performance test are given. The results show that the readout system has good linearity with the dynamic range of 16 fC, and low electronics noise of 1.2

Validation of numerical models of ceramic pin grid array packages

Thermal data for devices provided in manufacturers' data sheets are measured under idealized conditions and are not adequate to predict accurately junction temperature under other conditions. A validated model for the device, which can be employed in a variety of environments, is therefore required. This paper reports on the experimental and simulation work carried out to validate the thermal models for 180 and 224 pin cavity up ceramic pin grid array packages. The thermal test apparatus provides repeatable thermal resistance measurements and the known boundary conditions that are required for ease of simulation.