Abstract
Thermal data for devices provided in manufacturers' data sheets are measured under idealized conditions and are not adequate to predict accurately junction temperature under other conditions. A validated model for the device, which can be employed in a variety of environments, is therefore required. This paper reports on the experimental and simulation work carried out to validate the thermal models for 180 and 224 pin cavity up ceramic pin grid array packages. The thermal test apparatus provides repeatable thermal resistance measurements and the known boundary conditions that are required for ease of simulation.
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