Abstract
Several advanced packaging and interconnection technologies are currently under development to meet the requirements of complex, large and/or high-speed microelectronic integrated circuits (IC) and systems. These include the design of multilayer interconnection substrates (see Fig. 1.1) for Multichip Module (MCM) applications(1) and the development of multilayer ceramic pin grid array packages (see Fig. 1.2) for large-area die size, high pin count ICs.(2) A development road map(3) for single-chip packaging technologies is presented in Fig. 1.3.
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