Interconnect and Packaging Technologies for Realizing Miniaturized Smart Devices

Abstract

In order to become truly ubiquitous, the systems envisioned to create the ambient intelligence (AmI) landscape must be highly miniaturized and manufacturable at low cost. Together with system-on-a-chip (SoC) technology, interconnect and packaging technologies are key enabling technologies for realizing smart system-in-a-package (SiP) solutions. The realization of such devices requires new developments in the field of pack- aging and interconnection technologies. The continuing scaling trend in microelectronic circuit technology has a significant impact on the different integrated circuit (IC) interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so- called interconnect technology gap. Multilayer thin film technology is proposed as a bridge- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realization of true SiP solutions, combining multiple SoC IC's with other components and also integrating passive compon- ents in its layers. A further step is to use this technology to realize new functionalities on top of active wafers. These additional above-IC processed layers may be used for low loss, high speed on- chip interconnects, clock distribution circuits, efficient power/ground distribution, and to realize high Q inductors on chip.