Ceramic Package Research Articles

Acceleration Factor to relate Thermal Cycles to Power Cycles for Ceramic Ball Grid Area Array Packages

There is a need for a new Acceleration Factor (AF) that can relate Accelerated Thermal Cycle (ATC) fatigue life to Power Cycle (PC) fatigue life quickly and accurately in order to avoid over designing electronic packages for benign environments. An AF, such as the Norris-Landzberg AF, is only applicable when using it to predict fatigue life within the same environment, i.e. ATC to ATC or PC to PC. This work proposes an AF that takes into account the differences between ATC tests and PC tests for ceramic ball grid array (CBGA) packages by considering relevant design and environmental parameters. The new AF is based on relevant design parameters such as substrate size, substrate thermal conductivity, substrate thickness, coefficient of thermal (CTE) mismatch between the substrate and printed wiring board (PWB), PWB thickness, and environmental parameters such as temperature range (ΔT), frequency of cycles (f), and peak/junction temperature (Tj). Finite Element Models (FEM), experimental data, laser moiré interferometry, Design of Simulation (DOS), ANOVA, and regression analysis are used to develop the new AF. The new AF can be used to more accurately assess PC fatigue life from ATC tests so that expensive over-designing of electronic packages can be avoided for desktop/server/laptop applications.

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars. Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed. In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 mum) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16times increase over standard chip I/O, a 20times to 100times increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single virtual chip.

Elimination of Enhanced Low-Dose-Rate Sensitivity in Linear Bipolar Devices Using Silicon-Carbide Passivation

The type of final chip passivation layer used to fabricate linear bipolar circuits can have a major impact on the total dose hardness of some circuits. It is demonstrated that National Semiconductor Corporation linear bipolar devices fabricated with only an amorphous silicon carbide passivation layer do not exhibit enhanced low-dose-rate sensitivity (ELDRS), while devices from the same production lot fabricated with other types of passivation layers are ELDRS sensitive. SiC passivation possesses mechanical, electrical and chemical properties that make it compatible with linear device fabrication processes. These properties of SiC passivation layers, combined with the excellent radiation response of devices passivated with SiC, make SiC passivation layers a very attractive choice for devices packaged in either ceramic or plastic-encapsulated packages for use in space environments

Packaging of MMICs in multilayer LCP substrates

A 13-25-GHz GaAs bare die low noise amplifier is embedded inside a multilayer liquid crystal polymer (LCP) package made from seven layers of thin-film LCP. This new packaging topology has inherently unique properties that could make it an attractive alternative in some instances to traditional metal and ceramic hermetic packages. LCP is a near-hermetic material and its lamination process is at a relatively low temperature (285degC versus >800degC for ceramics). The active device is enclosed in a package consisting of several laminated C02 laser machined LCP superstrate layers. Measurements demonstrate that the LCP package and the 285degC packaging process have minimal effects on the monolithic microwave integrated circuit radio frequency (RF) performance. These findings show that both active and passive devices can be integrated together in a homogeneous laminated multilayer LCP package. This active/passive compatibility demonstrates a unique capability of LCP to form compact, vertically integrated (3-D) RF system-on-a-package modules

Localized CO 2 laser bonding process for MEMS packaging

The packaging poses a critical challenge for commercialization of MEMS products. Major problems with the packaging process include degraded reliability caused by the excess stress due to thermal mismatch and altered performance of the MEMS device after packaging caused by thermal exposure. The localized laser bonding technique for ceramic MEMS packaging to address above-mentioned challenges was investigated. A continuous wave CO 2 laser was used to locally heat sealing material for ceramic MEMS package lid to substrate bonding. To determine the laser power density and scanning speed, finite element analysis thermal models were constructed to simulate the localized laser bonding process. Further, the effect of external pressure at sealing ring on the bonding formation was studied. Pull testing results show that the scanning speed and external pressure have significant influence on the pull strength at the bonding interface. Cross-sectional microscopy of the bonding interface indicates that the packages bonded with relatively low scanning speed and external pressure conditions have higher bonding quality. This research demonstrates the potential of localized laser bonding process for ceramic MEMS packaging.

Planar antennas in LTCC technology with transceiver integration capability for ultra-wideband applications

We present two novel ultra-wideband (UWB) antennas embedded in a low-temperature co-fired ceramic (LTCC) package designed to house the UWB transceiver chip. Given their planar topology, circuit integration possibilities, and compact size, a partial ground-plane triangular monopole antenna (PGP-TM) and an antipodal Vivaldi antenna (AVA) are fully characterized. The performance in both the frequency and time domain are presented. The PGP-TM employs parasitic elements for tuning of the antenna's return loss. The PGP-TM antenna's measured 3.5-6.5-GHz bandwidth and omnidirectional pattern with 0-dB gain is suitable for the direct-sequence UWB (DS-UWB) lower subband, while the AVA's measured bandwidth of 3.35 GHz from 6.65 to 10 GHz and 5-dB gain make it suitable for the DS-UWB upper subband. The complete LTCC module containing the PGP-TM measures only 30 mmtimes25 mmtimes1.2 mm, while the AVA module measures 50 mmtimes25 mmtimes1.2 mm. Both LTCC modules can accommodate transceiver electronics because of a specially designed circuit feature. The effects of path loss can be canceled by combining these antennas in a transmission system. These are believed to be the first demonstrations of system-in-package technology for UWB applications

Shorter Field Life in Power Cycling for Organic Packages

The importance of power cycling as a mean of reliability assessment was revisited for flip chip plastic ball grid array (FC-PBGA) packages. Conventionally, reliability was addressed empirically through accelerated thermal cycling (ATC) because of its simplicity and conservative nature of life prediction. It was well accepted and served its role effectively for ceramic packages. In reality, an assembly is subjected to a power cycling, i.e., nonuniform temperature distribution with a chip as the only heat source and other components as heat dissipaters. This non-uniform temperature distribution and different coefficient of thermal expansion (CTE) of each component make the package deform differently than the case of uniform temperature in ATC. Higher substrate CTE in a plastic package generates double curvature in the package deformation and transfers higher stresses to the solder interconnects at the end of die. This mechanism makes the solder interconnects near the end of die edge fail earlier than those of the highest distance to neutral point. This phenomenon makes the interconnect fail earlier in power cycling than ATC. Apparently, we do not see this effect (the die shadow effect) in ceramic packages. In this work, a proper power cycling analysis procedure was proposed and conducted to predict solder fatigue life. An effort was made for FC-PBGA to show the possibility of shorter fatigue life in power cycling than the one of ATC. The procedure involves computational fluid dynamics (CFD) and finite element analyses (FEA). CFD analysis was used to extract transient heat transfer coefficients while subsequent FEA–thermal and FEA–structural analyses were used to calculate temperature distribution and strain energy density, respectively.

Influence of oxygen on the joining between copper and aluminium nitride

Aluminium nitride has been developed for electronic ceramic packaging applications because of its high thermal conductivity and high electrical resistivity. To improve the heat dissipation at the metal/ceramic interface, a high quality bonding between the substrate and the copper conductor is needed. This process requires a previous step of AIN pre-oxidation of the substrates by oxygen gas at 1200 °C, in order to form a thin layer of Al 2O 3 at the surface of AlN. The junction between Cu and the substrate is carried out at 1075 °C in controlled oxygen atmosphere which promote the oxidation of the copper and the formation of an eutectic phase which can form a strong junction with AlN via the layer of Al 2O 3. The goal of the current work is to study the influence of oxygen supplied by gaseous phase to form the exact amount of the eutectic phase needed to get a strong junction. First, in order to fix conditions for joining, the wetting behaviour of copper has been studied using the sessile drop method. The influence of oxygen brought by surrounding gas is given in terms of wettability of the liquid, interfacial tension and chemical reactions. According to previous results, copper foils and copper cylinders have been directly joined to AIN substrates. Interfacial reactions, mechanical and thermal properties have been investigated.

A manufacturable miniature electron beam column

A new and manufacturable miniature electron beam column has been designed, fabricated and tested. The low-voltage, all electrostatic, microfabricated electron beam column includes lenses consisting of bonded stacks of micro-machined silicon and glass. The lenses are microfabricated on 150 mm diameter substrates using semiconductor and bulk micro-machining fabrication processes. These processes are capable of fabricating columns with precise aperture diameters, and repeatable alignment tolerances. They also enable new designs that significantly increase the voltages at which miniature columns can reliably operate. The lenses are assembled onto a ceramic package using pick-and-place production tools. The package is fabricated using technologies that allow interconnects to be strategically distributed and encapsulated using high-resolution pattern transfer and enable fabricating small packages with high density routing and easy integration of buried and external passive and active devices, ground planes, and controlled impedance lines. Beam characterization of the column has begun and optimization continues. Preliminary spot size and resolution are presented.

Time-Lapse Measurements of Creep in Au-Sn Die Bonds

ABSTRACTGold-tin braze is the preferred material for attaching high-precision MEMS inertial sensors within hermetic ceramic packages. The bonds can be made at relatively low temperatures, are mechanically robust, and outgas at very low rates in vacuum sealed packages. There is one significant limitation to Au-Sn bonds, however. The thermal expansion coefficients of MEMS die and ceramic packages are not perfectly matched and temperature gradients occur when the assembly is cooled after brazing. As a result, there is considerable residual stress in the bonded assembly, which is accommodated to some extent by distortion of the sensor die. Over time, as these stresses relax, the distortion of the die changes, which causes the spacing between elements of the integral MEMS sensor to change as well. An important element of sensor-package design is insuring that stress relaxation effects do not cause the instrument to drift beyond its performance specification limits over a typical lifetime of 20 years.Even though Au-Sn has been used for decades to attach silicon chips to ceramic substrates, there is little data available, particularly at low temperatures. An oven, with a specially designed window, allowed in-situ measurements to be made as a function of temperature, joint thickness and load stress. Additionally, a MEMS device brazed to a package with Au-Sn has been measured interferometrically over time to quantify die distortion in a packaged application.

Application of life cycle assessment to improve the environmental performance of a ceramic tile packaging system

AbstractThe overall goal of this study was to evaluate the environmental performance of the process currently used to package and palletize ceramic floor and wall tiles, and to propose and analyse improvements from an environmental point of view. After developing a life cycle inventory of the primary and tertiary packaging, the life cycle assessment was applied according to mandatory and optional elements of ISO 14042. The results are presented in three parts: the first quantifies the environmental behaviour of the current packaging system, the second examines strategies focused on minimizing the environmental burdens of such critical elements, and the third quantifies the environmental improvements, compared with the initial situation, that are obtained with the application of each improvement. The simultaneous incorporation of all the proposed improvements into the packaging system can reduce impact within the 18–45% range, depending on the impact method that is applied. Copyright © 2005 John Wiley & Sons, Ltd.

Circuit model of microstrip patch antenna on ceramic land grid array package for antenna-chip codesign of highly integrated RF transceivers

This paper presents the circuit model of a microstrip patch antenna on a ceramic land grid array (CLGA) package for the antenna-chip codesign of a highly integrated radio-frequency (RF) transceiver. The microstrip patch antenna is fed by packaging interconnect components such as bond wires, signal traces, and vias in a ground-signal-ground (G-S-G) configuration from the carried chip. The circuit model that consists of RLC lumped elements of both microstrip patch antenna and feeding interconnect components has been developed with an emphasis on verifying existing or deriving analytical formulas. The RLC values of the microstrip patch antenna are calculated with our improvements to existing computer-aided design formulas, while the RLC values of the feeding interconnect components are calculated with more efforts. In particular the C values related to the vias and signal traces require to be calculated numerically and they are calculated here with the method of moments and the conformal mapping method, respectively. The circuit model is validated with numerical simulations (High Frequency Structure Simulator) and network analyzer measurements.

An All-Ceramic Interconnect for Use in Solid-Oxide Fuel Cell Stacks

AbstractThis article summarizes a unique approach in which all-ceramic interconnects are used in place of metal interconnects in solid-oxide fuel cell (SOFC) stacks. The approach combines advanced SOFC materials with the manufacturing technology and infrastructure established for multilayer ceramic (MLC) packaging for the microelectronics industry. The MLC interconnect is fabricated using multiple layers of yttria-stabilized zirconia (YSZ) tape, with each layer containing conductive vias to provide for electrical current flow through the interconnect. The all-ceramic interconnect design facilitates uniform distribution of air and fuel gas to the respective electrodes of adjacent cells. The multilayer interconnects are fabricated using traditional MLC manufacturing processes. A detailed description of the processes for fabricating the all-ceramic interconnect is presented.To aid in moving from prototype fabrication to commercialization of these fuel cell systems, a detailed cost model has been used as a roadmap for commercial stack development. Cost model projections are presented for three different interconnect footprint sizes. These projections show an SOFC stack cost of less than $150 per kilowatt for the optimized SOFC stack design produced at high volume.

Deposition and Single-Step Processing of YBCO Thick Films for Multilayered Electronics

The goal of this project was to successfully co fi re a screen-printed yttrium bar­ ium copper oxide (YBCO) superconductor onto a low-temperature co fi red ceramic (LTCC) substrate. The purpose was to investigate the compatibility of thick- fi lm, high-temperature superconductors with multilayered ceramic (MLC) packages for cryogenic applications. Paste consisting of standard organics and YBCO powder of -325 mesh particle size was screen-printed onto Dupont 951 Green Tape. The system was co fi red at temperatures ranging from 925°C to 975°C. The quality of the co fi red system was characterized in several ways: Meissner diamagnetism, scanning electron microscopy, x-ray diffraction, and AC susceptibility tests were performed to determine the superconducting capability of the system. Samples co fi red at 950°C retained some superconductivity after fi ring and showed the best compromise be­tween sintering and degradation.

Plastic-Encapsulated Microcircuits (PEMs) Failure Analysis

Abstract Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

Development of CMOS integrated optical receiver for short‐range data communication

AbstractReduction of the size and cost of optical receivers is important to the proliferation of optical communications technology for short‐distance communications. In the present research, an integrated optical receiver is fabricated with a standard 0.35‐µm CMOS process targeting the POF optical transmission system. A photodiode, a trans‐impedance amplifier, a limiting amplifier, and a buffer are integrated in this optical receiver. The photodiode is formed with an N‐well and a P‐diffused layer of stripe configuration and has an optical receiving surface area of 150 × 150 µm and a response sensitivity of about 0.04 A/W (at a wavelength of 650 nm). In the CMOS process, the large junction capacitance of the photodiode is problematic. Therefore, the input impedance of the circuit is lowered by means of an RGC‐type trans‐impedance amplifier and LC resonance is suppressed by optimization of the package and circuit. The chip is mounted in a small ceramic package for measurement. Excellent eye patterns are obtained. The minimum receiving sensitivity for a bit error rate of less than 10−9 is −10 dBm at 600 Mbit/s and −4.5 dBm at 1 Gbit/s. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(12): 10–18, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20099

Integrated Circuit Ceramic Ball Grid Array Package Antenna

The recent advances in such highly integrated RF transceivers as radio system-on-chip and radio system-in-package have called for the parallel development of compact and efficient antennas. This paper addresses the development of a new type of dielectric chip antenna known as integrated circuit package antenna (ICPA) for highly integrated RF transceivers. A compact ICPA of this type has, for the first time, been designed and fabricated in a ceramic ball grid array (CBGA) package format. The novel ICPA, except economical advantage of mass production and automatic assembly, has potential benefit to the system-level board miniaturization and the system-level manufacturing facilitation. The simulated and measured antenna performance of the ICPA is presented. The effects of the different physical parts of the ICPA on the antenna performance are investigated. Results show that the ICPA achieved impedance bandwidth of 4.1% and radiation efficiency of 72%, and gain of 4.8 dBi at 5.715 GHz.

Microstructural Effects on Microwave Properties of Low-Temperature Cofired Ceramic Striplines: Experiments and Modeling

The effect of microstructure on microwave properties of low-temperature cofired ceramic (LTCC) stripline packages was studied with experiments and simulations. Microstructure was controlled experimentally by modifying organic compositions and heating procedures. Pores existing at the conductor/dielectric interface and inside the conductor line affected the microwave properties, such as the effective dielectric constant (εeff), the effective conductivity (σeff), and the unloaded quality factor (QU) of the stripline packages. The models for simulation were introduced with a finite-element method using high-frequency simulation software (HFSS). Simulation results showed that the pores existing at the interface made QU increase by 7%–8% while [alt epsilon]eff decrease by more than 10%. Pores inside the conductor line made σeff and QU decrease. The proposed models and simulation results will contribute to improving future designs and manufacturing of LTCC microwave applications.

Gold Dendrite Simulation: Root Cause Determination

While dendritic growth for Ag, Sn, and other metals provides jeopardy for the exterior of packaged integrated circuits, we observed Au dendrites inside ceramic packages. The key factors controlling growth kinetics are a combination of bias and two residual chemicals: one hygroscopic component from the die attach material, and gold plating salts. We found dendritic growth rate to be linear with plating salt concentration during laboratory simulations, but were unable to measure the current density dependence. However, the key factor was the presence or absence of residual nonylphenol, tracked down to an inadequate die attach bake schedule. Laboratory simulations produced the same dendrite morphology as seen for failed units. Furthermore, we found dendritic growth would occur only if all three factors were present-bias, nonylphenol, and the plating salts.