Ceramic Package Research Articles

Development of Miniature Quad SAW Filter Bank based on PCB Substrate

This paper describes the development of a new <TEX>$5.0{\times}3.2mm$</TEX> SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of <TEX>$LiTaO_3$</TEX> SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini <TEX>$5.0{\times}3.2mm$</TEX> filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

Low‐loss and broadband BGA package transition for LTCC‐SiP applications

AbstractA high‐performance broadband ball‐grid‐array (BGA) package transition was designed and implemented from DC up to the Ka‐band frequencies. The vertical BGA‐via transition path starts from an organic motherboard (PCB) and ends at the top surface of a low‐temperature cofired ceramic module package. To assess solder joint reliability, large plastic‐core solder balls with a diameter of 800 μm were employed. The measured insertion loss of the entire vertical transition path, including feedlines, was better than 0.5 dB (1 dB) up to 25 GHz (29 GHz). Moreover, an equivalent circuit model for the complete transition path was developed. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1036–1040, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23276

Analysis and Prediction of Vibration-Induced Solder Joint Failure for a Ceramic Column Grid Array Package

Solder joint fatigue failure under vibration loading continues to be a concern in microelectronic industry. Existing literature has not adequately addressed high-cycle fatigue failure of high-lead solder joints, especially under a broad spectrum of vibration frequencies. Also, damage mapping across solder joints in an area-array package has not been effectively studied using numerical models and experimental cross sectioning. This paper aims to develop an experimental and modeling approach that can accurately determine the solder joint behavior of electronic components under vibration conditions. In particular, this paper discusses the out-of-plane sinusoidal vibration experiments at 1G, numerical modeling, and fatigue life prediction for a 42.5×42.5×4mm3 1089 input∕output ceramic column grid array (CCGA) package on a 133×56×2.8mm3 FR4 board. Detailed investigation and characterization involving dye-and-pry analysis, microstructural examination, and numerical modeling enabled the development of a high-cycle stress-based equation for lead-containing CCGA under sinusoidal loading. The developed approach has been applied to a number of cases including a CCGA package with a heat sink as well as a CCGA package subjected to frequency sweeps. It is seen that the predictions from the developed model agree well with experimental data and that the developed model can map the evolution of solder damage across all solder joints and can also provide important design recommendations in terms of solder joint location as well as heat sink attachment.

Modified Engelmaier’s model taking account of different stress levels

In this paper, the solder fatigue model created by Werner Engelmaier is modified so that it takes better into account the different stress levels the solder material experiences. This is accomplished by replacing the fatigue ductility constant by a correction term that is temperature- excursion- range-dependent. In order to obtain the correction term, the effect of the temperature cycling profile on lifetime is studied. The correction term obtained is package type specific. More compliant plastic packages with a small coefficient of expansion mismatch with the organic printed wiring board are handled separately, and stiff ceramic packages assembled on an organic board – resulting in a large CTE mismatch – are considered as another entity. Correction terms for both lead-free and tin–lead solder materials are given. This is necessary as the creep characteristics of the solders are different. Comparing solder material specific correction terms makes it possible to determine which solder material performs best in a certain environment and a given assembly type. In the case of ceramic packages, the transition where a eutectic tin–lead solder becomes superior to a SnAgCu solder is expected to take place when temperature excursions are smaller than ca. 70 °C. This indicates that although in a highly accelerated stress test, lead-free solders may be inferior compared to tin–lead solders, in the real field environment, the situation may be reversed.

Characterization of miniaturized one-side-electrode-type fluid-based inclinometer

In this study, electrical double-layer theory is applied to realize a one-side-electrode-type fluid-based inclinometer combined with complementary metal oxide semiconductor (CMOS) circuitry. Substrate penetration lithography was applied in the fabrication of high-aspect-ratio SU-8 container molds, and molds with heights 1.0 mm were fabricated. Polydimethylsiloxane (PDMS) was used as the container material, and electrodes were fabricated on a ceramic substrate. Considering the electrical double-layer property, low surface tension, the dielectric constant and the problem of volatilization, methanol and propylene carbonate were tested as electrolytes. A charge-balanced capacitance–voltage ( C– V) conversion circuit was designed as a detection circuit for this sensor and it was fabricated using 0.35 μm CMOS technology. The sensor part and detection circuit were integrated in one ceramic packaging for realize a miniaturization of inclination sensor system. To overcome the surface tension of the PDMS surface, silicone oil was injected in the container to cover the entire inner surface so that the movement of solution in the container became smooth. The linearity of the analog output of ±60° inclination for container dimensions of Ø 4.0 mm × 1.0 mm (diameter × thickness) was less than 6%/F.S. The minimum moving angle and response time were 0.4° and 0.9 s, respectively, when propylene carbonate was used as the electrolyte. The change in temperature did not affect the output voltage of the sensor between 0 and 50 °C. The effect of vibration was demonstrated in this paper.

Development of Light Sources by Large-Scale Integrated Light-Emitting Diodes

We have demonstrated large-scale integrated light-emitting diodes (LSILEDs) by using direct flip-chip bonding (DFCB) technique on a size of 30 × 40 mm2 ceramic package. Radiant flux measured at DC current of 9.1 A and forward voltage of 4.0 V was 3.3 W. Luminous flux, luminous efficacy and color-rendering index of white LED fabricated with the LSILED as the excitation source measured at DC current of 9.1 A and forward voltage of 4.0 V was 766 lm, 21.0 lm/W, and 82, respectively. The LSILED is very promising as a compact, high dense and high luminous flux white light source.

Analysis of Chip/Bump/Ceramic Interface of Flip-Chip Bonded LED Directly on Ceramic Packages

Analysis of Chip/Bump/Ceramic Interface of Flip-Chip Bonded LED Directly on Ceramic Packages

Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">*</sub> Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics unit and an advanced cryptographic unit which provides high enough bandwidth to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments' 65 nm 11LM triple-Vt CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.

Multiple beam sub-80-nm lithography with miniature electron beam column arrays

Miniature electron beam columns have the potential for high resolution, high throughput maskless lithography applications because they can be scaled in number to form high density column arrays with low fabrication costs. This is achieved using manufacturing techniques that leverage rf packaging technologies and standard bulk micromachining and integrated circuit fabrication processes to produce reliable components with repeatable performance characteristics. A 1×4 electrostatic column array designed to target the 45nm node has been built using monolithically fabricated lenses and packages. The lenses, which consist of stacks of patterned silicon and insulator, are mounted to a ceramic package. Internal to the package are traces which carry all interconnects to drive the column. Each column in the array is individually correctable. The monolithic lens design simplifies the pick-and-place assembly of high density column arrays and enables precise column-to-column registration. The design also facilitates scaling up of the column density to achieve higher throughput, and simulations presented previously suggest that the design can be extended to meet the 22nm resolution requirement. This article presents the first results from simultaneous multiple beam lithography using miniature column arrays. Independent patterns were exposed synchronously at 1keV using two columns in a 1×4 monolithic column array, resulting in 75nm features written into ZEP-520A resist. Other experiments suggest reliable high voltage lens performance and good beam current and position stability. These preliminary results from arrays of limited numbers of columns demonstrate progress toward the development of full-scale direct write lithography systems driven by miniature column arrays.

A micro rate gyroscope based on the SAW gyroscopic effect

We propose a micro rate gyroscope (MRG) based on the surface acoustic wave (SAW) gyroscopic effect for extremely high-shock military applications. We not only derived theoretically the SAW gyroscopic gain factor in a ST-cut quartz by introducing a wave velocity ratio and the perturbation method, but also verified this gain factor by experiment. The proposed SAWMRG, which consists of two delay-line oscillators, operates as a differential scheme. To estimate an inherent insertion loss, we adopted the equivalent circuit model in the design process of the delay line. The 9 × 9 mm2 SAWMRG was fabricated on a ST-cut quartz and loaded into a specially designed low temperature co-fired ceramic (LTCC) package to ensure good RF characteristics. The center frequency and the insertion loss of the delay line are measured at 98.6 MHz and 15.2 dB, respectively. We evaluated the performance of the SAWMRG, using a rate table and stochastic noise analysis, revealing a sensitivity of 0.431 Hz deg−1 s−1 in the angular rates up to 2000 deg s−1 and a white noise of 0.55 deg s−1 Hz−1/2, respectively. Consequently the feasibility of the proposed SAWMRG was verified through a set of performance evaluations, confirming the theoretical predictions.

A silicon carbide capacitive pressure sensor for in-cylinder pressure measurement

This paper reports a research prototype of a low-cost, miniature, mass-producible sensor for measurement of high-pressure at operating temperatures of 300–600°C, e.g., in-cylinder engine pressure monitoring applications. This all-silicon carbide (SiC) capacitive sensor, i.e., a SiC diaphragm on a SiC substrate, takes advantage of the excellent harsh-environment material properties of SiC and is fabricated by surface micromachining. The sensor is packaged in a high-temperature ceramic package and characterized under static pressures of up to ∼5MPa (700psi) and temperatures of up to 574°C in a custom chamber. An instrumentation amplifier integrated circuit is used to convert capacitance into voltage for measurements up to 300°C; beyond 300°C, the capacitance is measured directly from an array of identical sensor elements using a LCZ meter. After high-temperature soaking and several tens of temperature/pressure cycles, packaged sensors continue to show stable operation. For monitoring the dynamic cylinder pressure in the combustion chamber, the sensor is packaged in a custom probe and inserted into the cylinder head of a research internal combustion engine. The sensor efficacy is verified against the reference probe used for monitoring pressure in the research engine.

Analysis of Novel Packaging Techniques for High Power Electronics in SiC

A novel high temperature wire bondless packaging technique is numerically investigated in this paper. Extraction of device effective resistivity with temperature from numerical characteristics of 1.2kV 4H-SiC MOSFETs at a current density of 400A/cm2 have demonstrated a T−2 temperature dependence. Electro-thermal finite element analysis (FEA) of 1.2kV 4H-SiC MOSFETs sandwiched between two etched direct-bonded-copper substrate tiles has been performed. The thermal resistance of the ceramic sandwich package shows a 75% reduction in thermal resistance compared to conventional wire bonded assemblies. Mechanical analysis of the assembly has been used to investigate the residual stresses in the SiC dies at room temperature, which are then alleviated at higher temperatures during device operation. Mismatch of the expansion coefficients of the auxiliary materials in the assembly result in elevated stresses at full load operation, however these are well below the tensile strength of the respective materials and hence do not compromise the mechanical integrity of the package.

Design and synthesis of fusible glass solder with previously assigned properties

Experimentally substantiated recommendations on selecting compositions and technologies for synthesis of glass solders with assigned properties within the soldering temperature limits of 390–450°C and CLTE of (60–70) × 10−7 K−1, designed for hermetically sealing the ceramic packages of integrated microcircuits are reported.

Thermal design of ceramic packages for high power light-emitting diodes

Ceramic packages with different paths of thermal dissipation were designed by a simulation using the finite-volume method. Thermal resistances of the packages were obtained from the calculation of temperatures of LED (light emitting diode) chips. It was shown that the thermal characteristics of LED packages were strongly affected by the contact area of a thermal via in contact with a LED chip rather than that in contact with a ceramic mould. Ceramic LED packages were fabricated and characterized. A deviation of simulated results from experimental results was found. The difference was attributed to the poor contact roughness between the LED chip and the thermal via.

세라믹 패키지를 이용한 표면실장형 다이오드의 제작과 특성평가

Generally, a diode package consists of the synthetic resin that has good durability but low thermal conductivity. The surface mounted type fast recovery diode was fabricated by using ceramic package. Its main manufacture processes are composed of soldering, sillicon coating and side termination. And it has various advantages that diode is small, easy manufacture and fast cooling. The electric characteristics of the diode such as reverse recovery time, breakdown voltage, forward voltage, and leakage current were 5.28 ns, 1322 V, 1.08 V, , respectively.

An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls

Although accelerated thermal cycling has been widely used in electronics industry to qualify electronic packages, efforts to reduce the time and cost associated with such qualification techniques are continuously being sought. This paper outlines a laser-moiré based experimental technique to quickly assess the thermal cycling reliability of microelectronic packages. Unlike accelerated thermal cycling that takes several months to complete, the proposed technique takes one to two weeks to complete and does not suffer from various modeling assumptions used in finite-element simulations. The developed technique has been used to determine the thermomechanical reliability of organic and ceramic ball grid array packages, and it is shown that the number of cycles determined by the proposed technique is comparable to the number of cycles determined through accelerated thermal cycling.

Micro Via-Hole Punching of LTCC-PET Double Layer Sheets

In low temperature co-fired ceramic (LTCC) packaging which offers a good performance to produce multilayer structures with electronic circuits and components, the via-hole fabrication of LTCC ceramic-PET double layer sheets (green sheets or green tapes) by micro-scale punching plays an important role in providing an electric path for the interconnection between layers. Although conventional punching has been used widely and many researchers have provided useful insights of the process, they are restricted to the punching of single layer material. This paper discusses the characteristic of micro via-hole punching of double layer sheets and the optimum process condition for via-holes of good quality. Workpiece (double layer sheet) used in the present investigation consists of LTCC ceramic composite material layer (ceramic layer) of 20~100*m in thickness and PET layer of 38 and 75*m in thickness by tape-casting. The diameter of via-holes ranges from 100~300*m.

Thermal analysis of high power GaN-based LEDs with ceramic package

In this paper we present thermal analysis of three kinds of ceramic package designs for high power LEDs. The analysis was made by transient thermal measurement and thermal simulation using the Finite Volume Method. The three ceramic packages under investigation employ same configuration of GaN-based chip, but they have different size and distribution of thermal vias. Three designs of LED packages resulted in significantly different thermal behaviors. Thermal behaviors, described as thermal resistance, of the three packaging designs were compared and evaluated as functions of bulk thermal resistance, spreading resistance, and surface roughness. The deviation between the simulated results and measured data were attributed to the different surface roughness in the interfaces between the packaging components. It was demonstrated that the junction temperature decreases with the effective contact area ratio in the LED packages.

Sub- 100-nm lithography with miniature electron beam columns

Miniature low-voltage electron beam columns are well suited for low cost imaging and high throughput direct-write lithography applications. Previous generations of miniature columns have demonstrated high-resolution imaging and proof-of-concept lithography. However, those columns suffered from difficult fabrication techniques and costly assembly, making them impractical for broad application. A new type of miniature electron beam column has been developed with the goal of manufacturability using bonded stacks of batch fabricated silicon lenses and glass insulators. Bulk micromachining and integrated chip fabrication techniques facilitate the fabrication of columns with precise aperture-to-aperture alignment and high aperture circularity. The lens stacks are bonded to a multilayer ceramic package with embedded interconnects. This approach enables a small package that can include buried internal and external passive and active devices, ground planes, and controlled impedance-matched lines. The package is fully scalable for continued miniaturization, and can be easily designed to accommodate 1×4 or larger modules of individually correctable columns for arrayed operation. This article presents the first lithography results with these miniature columns over a beam energy range of 0.5–2keV. Patterns were written into ∼45nm ZEP-520A resist using a raster-scan writing strategy. A nominal dose of 7μC∕cm2 yielded 90nm isolated and 180nm line-space patterns. High-resolution images resolved &amp;lt;35nm features.

Dual-Band Microstrip Bandpass Filter Using Stepped-Impedance Resonators With New Coupling Schemes

A microstrip bandpass filter using stepped-impedance resonators is designed in low-temperature co-fired ceramic technology for dual-band applications at 2.4 and 5.2 GHz. New coupling schemes are proposed to replace the normal counterparts. It is found that the new coupling scheme for the interstages can enhance the layout compactness of the bandpass filter; while the new coupling scheme at the input and output can improve the performance of the bandpass filter. To validate the design and analysis, a prototype of the bandpass filter was fabricated and measured. It is shown that the measured and simulated performances are in good agreement. The prototype of the bandpass filter achieved insertion loss of 1.25 and 1.87 dB, S11 of -29 and -40 dB, and bandwidth of 21% and 12.7% at 2.4 and 5.2 GHz, respectively. The bandpass filter is further studied for a single-package solution of dual-band radio transceivers. The bandpass filter is, therefore, integrated into a ceramic ball grid array package. The integration is analyzed with an emphasis on the connection of the bandpass filter to the antenna and to the transceiver die