Ceramic Ball Grid Array Research Articles

P-WLCSP: 6-Side Protected WLCSP

The first silicon demonstration of 300mm P-WLCSP was introduced in 2021 at the 54th International Symposium on Microelectronics. This paper reports further developments and new test results for this low cost WLCSP approach to fully protected CSP. The paper briefly summarizes the evolution of protected CSP technology evolution as an introduction for a more extensive discussion of P-WLCSP. With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package) and for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to 1 sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP (non WF) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding operations required in a FO process that can be eliminated in a WLCSP protected FI process. American Semiconductor’s Semiconductor-on-Polymerâ?¢ (SoPâ?¢) 300mm FleX-TM P-WLCSP is an advanced packaging process optimized for protected fan-in. P-WLSCP ultra-thin fully protected chips will be shown from a wafer level process. Process development progress and test results will be presented.

Research on Processability and Transmission Performance of Low Temperature Co-Fired Ceramic Ball Grid Array Packaging Based on Electroless Plating Surface Modification for Microwave Transceiver Circuits.

A microwave transmitter/receiver using the low-temperature co-fired ceramic substrate and ball grid array packaging demonstrates superior properties, including high integration, miniaturization, and high electromagnetic shielding. However, it holds limitations of inadequate hermeticity (that is, gas or moist impermeability), high cost, and low reproducibility. In this work, we aim to overcome these difficulties by introducing a new packing technique. The packaging utilizes an electroless plated Ni/Pd/Au surface, resulting in a significant enhancement of the packaging hermeticity by orders of magnitude, approaching the level of <5 × 10-9 Pa·m3/s. Both Sn63Pb37 and Au80Sn20 solder alloys demonstrate exceptional solderability, attributed to Pd atoms diffusing to the Au layer during soldering at 310 °C. A reliability test of the packaging shows that the shear strength of the solder balls drops after thermal shocks but negligibly affects the hermeticity of the packaging. Furthermore, a meticulously designed internal vertical interconnect structure and I/O interconnections were engineered in the ball grid array packaging, showcasing excellent transmission characteristics within the 10-40 GHz frequency range while ensuring effective isolation between ports.

A new type of spinel ceramic for CBGA package

High thermal conductivity with HITCE are highly required for microwave dielectric ceramics for CBGA electronic packaging applications. In this work, AAl2O4-x wt. % (Li2CO3-Al2O3-SiO2) (A = Zn, Mg) ceramics with spinel structure were synthesized through a conventional solid-state reaction method. The coefficient of thermal expansion of the ceramics are much higher than spinel ceramics because of the addition of Li2CO3-Al2O3-SiO2 additive. Meanwhile, the high thermal conductivity ceramics are also obtained due to the high thermal conductivity of its spinel structure and dense microstructure. Especially, ZnAl2O4-5 wt. % (Li2CO3-Al2O3-SiO2) compound exhibits thermal conductivity of 13.531 W/mK, TCE value of 8.65ⅹ10−6 K−1 (30–490 ℃), dielectric constant of 8.40 and dielectric loss of 4.40ⅹ10−4. And MgAl2O4-10 wt. % (Li2CO3-Al2O3-SiO2) compound exhibits thermal conductivity of 16.8 W/mK, TCE value of 8.9ⅹ10−6 K−1 (30–500 ℃), dielectric constant of 7.89 and dielectric loss of 8.90ⅹ10−3. The excellent thermal and dielectric properties give it a great potential in Ceramic Ball Grid Array electronic packaging applications.

Protected Wafer Level Chip Scale Packaging (P-WLCSP)

With the advent of bumped die, new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip), CBGA (ceramic ball grid array), and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), was built on the wafer with no active side protection, evolving to single sided protection from a package built on the wafer3 , which transitioned to redistribution PSB (passivation stress buffer)4 . PSBs were implemented in FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability, performance evolved to CSP5 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. An example of fully protected die CSP (without substrates or leadframes) encapsulated in mold compound is M-series utilizing a FO (fan out) processes and eWLB.6,7 To obtain higher reliability 6-sided die protection afforded by FO processes require die reconstitution, expensive tapes, molding, and other operations which can feasibly be eliminated in a WLCSP protected FI process assuming full encapsulation can be attained on the original device wafer. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected fan-in. SoP-TM produces the thinnest and lowest cost fully protected FI. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This paper includes background on the evolution of CSP, comparison of SOTA (state of the art) FI processes including SoP-TM and builds on low-cost wafer level adaptive process works and reliability data presented on the new SoP-TM process earlier this year.8,9 First article electrical reliability test data for P-WLCSP, adaptive processing of micro-bump pads, and potential applications in hybrid modules will be shown.

The Terminal Protection Effect by Underfill Material on the Ceramic BGA Package Mounting Sample under Thermal Shock Cycling

宇宙用LSIパッケージはキャビティ内にチップを気密封止するセラミックパッケージが多く使用される。近年は多ピン化や小型化のためBall-Grid-Array (BGA) パッケージなどが多くなり，プリント配線板への実装において熱サイクル耐性が主要課題である。熱サイクル耐性向上のためアンダーフィル材が適用されることが多いが，セラミックBGAパッケージでは熱サイクル試験の早期にパッケージ底面からアンダーフィルが剥離する場合がある。3,000サイクル以上の熱サイクル負荷に対して，今回適用したアンダーフィル材が剥離せず端子を保護したこと，および端子以外で観察された不良の兆候について報告する。

Numerical and Experimental Investigations of the Thermal Fatigue Lifetime of CBGA Packages

A thermal fatigue lifetime prediction model of ceramic ball grid array (CBGA) packages is proposed based on the Darveaux model. A finite element model of the CBGA packages is established, and the Anand model is used to describe the viscoplasticity of the CBGA solder. The average viscoplastic strain energy density increment ΔWave of the CBGA packages is obtained using a finite element simulation, and the influence of different structural parameters on the ΔWave is analyzed. A simplified analytical model of the ΔWave is established using the simulation data. The thermal fatigue lifetime of CBGA packages is obtained from a thermal cycling test. The Darveaux lifetime prediction model is modified based on the thermal fatigue lifetime obtained from the experiment and the corresponding ΔWave. A validation test is conducted to verify the accuracy of the thermal fatigue lifetime prediction model of the CBGA packages. This proposed model can be used in engineering to evaluate the lifetime of CBGA packages.

Advanced Protected Fan-In WLCSP

ABSTRACT With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to single sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP4 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding, and other operations generally required in a FO process which can feasibly be eliminated in a WLCSP protected FI process. American Semiconductor's Semiconductor-on-Polymer™ (SoP™) 300mm FleX-TM WLCSP is an advanced packaging process optimized for protected fan-in. FleX-TM produces the thinnest and lowest cost protected FI the industry today. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This article includes background on the evolution of CSP and the comparison of SOTA (state of the art) FI processes including FleX-TM.

Influence of ceramic substrate quality on CBGA assembly reliability

The highly air-sealed ceramic ball grid array (CBGA) package is more and more popular in the aerospace and other military industries, the quality of its ceramic substrate can largely determine the CBGA package reliability and further product performance. Thus, two kinds of high temperature co-fired ceramic (HTCC) substrates from A and B suppliers were employed to assess different CBGA assembly performances in this work. The results were found that the pads of A and B substrates owned similar morphology feature and mean size. After re-balling process, comparing to that of B substrate, the mean deviation from coplanarity of A substrate was higher, but the shear strength of solder balls on A substrate was better and more stable. Through analyzing shear fracture faces, the dimples were discovered and ductile fracture mode was verified. Additionally, the microstructure of CBGA package was observed after soldering process, the metallurgical reactions at solder joints occurred and the interfacial intermetallic compound (IMC) layers formed. When 100 cycles test from −55 to 85 °C finished, the metallographic analysis was obtained that the solder joint in the corner of CBGA package produced deformation and microcracks due to high thermal stress, the microcrack result was better with the usage of A substrate. The series of detection methods and means might provide the effective help for CBGA engineering application.

Experimental SAC305 Shear Stress–Strain Hysteresis Loop Construction Using Hall's One-Dimensional Model Based on Strain Gages Measurements

Temperature-induced solder joint fatigue is a main reliability concern for aerospace and military industries whose electronic equipment used in the field is required to remain functional under harsh loadings. Due to the RoHS directive, which eventually will prevent lead from being utilized in electronic systems, there is a need for a better understanding of lead-free thermomechanical behavior when subjected to temperature variations. Characterizing solder joints properties remains a challenge as viscoplastic behavior during thermal cycling is complex, and their small dimensions prevent direct measurements from being performed. This paper reports the experimentation based on strain gage measurements, allowing the construction of the shear stress–strain hysteresis loop corresponding to Sn3.0Ag0.5Cu (SAC305) solder joints behavior during thermomechanical loading. This methodology, initially developed in 1984 by Hall for Sn60Pb40 interconnects, allows the measurement of the strain energy density dissipated during temperature cycles. Custom daisy-chained 76 I/O ceramic ball grid array (CBGA76) components were designed and assembled on flame retardant (FR-4) multilayered printed circuit boards (PCB). Four strain gages were specifically placed at the center of the assembly on top and bottom faces of both PCB and CBGA76 component. The assembly was subjected to temperature cycles and the SAC305 solder joints shear stress–strain hysteresis loop was plotted. The correlation between the measured strain energy density and measured lifetime corresponds to one point of the energy based fatigue curve for SAC305 solder joints. The hysteresis loop also provides the necessary data to derive SAC305 solder joints constitutive laws.

Accelerated temperature cycling induced strain and failure behaviour for BGA assemblies of third generation high Ag content Pb-free solder alloys

In severe operation environments where extreme thermal cycles and long dwells are common, such as the engine compartment of motor vehicles, solder alloys resistant to fatigue under thermomechanical stimuli are required. With this in mind, new third generation lead free alloys are being designed to enhance the toughness of interfacial intermetallic layer (IML), and solid solution strengthening is introduced to compensate for the strength loss due to Ag3Sn particle coarsening. In this paper, the reliability of ceramic Ball Grid Array (BGA) assemblies using third generation lead-free alloys under various strain levels and Accelerated Temperature Cycling (ATC) profiles, 0/100 °C and −40/125 °C, are presented. Failure analysis was conducted and cracking along the IML at the solder/package interface was determined to be the root failure mechanism. The ATC test results indicate that the induced fatigue strain on each ring of the BGAs is a function of maximum dwell temperature, alloy choice and temperature change (ΔT) within the thermal cycle, and this is noted to have a significant influence on characteristic lifetimes. Results correlate well with the Coffin-Manson model, and activation energies (EA) were determined to predict the reliability of the electronic on the premise of the same predominant failure mechanism.

Influence of Y2O3 Addition on Crystallization, Thermal, Mechanical, and Electrical Properties of BaO-Al2O3-B2O3-SiO2 Glass–Ceramic for Ceramic Ball Grid Array Package

Y2O3 addition has a significant influence on the crystallization, thermal, mechanical, and electrical properties of BaO-Al2O3 -B2O3 -SiO2 (BABS) glass–ceramics. Semi-quantitative calculation based on x-ray diffraction demonstrated that with increasing Y2O3 content, both the crystallinity and the phase content of cristobalite gradually decreased. It is effective for the additive Y2O3 to inhibit the formation of cristobalite phase with a large coefficient of thermal expansion value. The flexural strength and the Young’s modulus, thus, are remarkably increased from 140 MPa to 200 MPa and 56.5 GPa to 63.7 GPa, respectively. Also, the sintering kinetics of BABS glass–ceramics with various Y2O3 were investigated using the isothermal sintering shrinkage curve at different sintering temperatures. The sintering activation energy Q sharply decreased from 99.8 kJ/mol to 81.5 kJ/mol when 0.2% Y2O3 was added, which indicated that a small amount of Y2O3 could effectively promote the sintering procedure of BABS glass–ceramics.

Stencil Print solutions for Advance Packaging Applications

Abstract This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging. As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high-performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um–40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package. Cavity technology can be an effective solution in reducing the total assembled PCB thickness (Z-height), most importantly, on designs utilizing taller - stacked devices. Traditionally, dipping process or dispensing process was used to deposit solder paste, flux, or glue on uneven surfaces. However, this takes a longer time when compared to printing using a stencil printer. Reservoir printing using a stencil printer has greater potential in such application. Extensive work has been done in the past to print glue, solder paste and/or flux into cavities using reservoir printing. This paper focuses on printing solder paste into multiple cavities (stencil pockets) with depths ranging from 355 microns to 450 microns, and with varying cavity size, wall angles and various stencil thicknesses ranging from 100 microns to 150 microns. Apertures varying in area ratio were placed in these cavities and experiments were conducted to analyze the print performance of the stencils. As the size of the components and boards/substrates gets smaller - closer placement of components to the cavity (stencil pocket) walls needed to be assessed as well. These applications, the associated stencil design and print results were discussed in detail in this paper.

Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly

Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

Process and Evaluation of High Reliability Reworkable Edge Bond Adhesives for Large Area BGA Applications

Reworkable underfills and edge bond adhesives are finding increasing utility in high reliability and harsh environment applications. The ASICs and FPGAs often used in these systems typically require designs incorporating large BGAs and ceramic BGAs. For these high reliability and harsh environment applications, these packages typically require underfill or edge bond materials to achieve the needed thermal cycle, mechanical shock and vibration reliability. Moreover, these applications often incorporate high dollar value printed circuit boards (on the order of thousands or tens of thousands of dollars per PCB) hence the need to rework these assemblies and maintain the integrity of the PCB and high dollar value BGAs. This further complicates the underfill requirements with a reworkability component. Reworkable underfills introduce a number of process issues that can result in significant variability in reliability performance. In contrast, edge bond adhesives provide a high reliability solution with substantial benefits over underfills. One interesting question for the large area BGA applications of reworkable underfills and edge bond materials is the comparison of their reliability performance. This paper presents a study of reliability comparison between two robust selected reworkable underfill and edge bond adhesive in a test vehicle including 11mm, 13mm, and 27mm large area BGAs. Process development for those large area BGA applications was also conducted on the underfill process and edge bond process to determine optimum process conditions. For underfill processing, establishing an underfill process that minimizing/eliminates underfill voids is critical. For edge bond processing, establishing an edge bond that maximizes bond area without encapsulating the solder balls is key to achieving high reliability. In addition, this paper also presents a study of new high performance reworkable edge bond materials designed to improve the reliability of large area BGAs and ceramic BGAs assemblies while maintaining good reworkablity. Four edge bond materials (commercially available) were studied and compared for a test vehicles with 12mm BGAs. The reliability testing protocol included board level thermal cycling (−40 to 125°C), mechanical drop testing (2900 G), and random vibration testing (3 G, 10 – 1000 Hz).

Microelectronics packaging technology roadmaps, assembly reliability, and prognostics

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies.

An ultra flat phased array Ku-band antenna with integrated receivers in SiGe BiCMOS

A highly integrated Ku-band (10.7–12.75 GHz) planar phased array receiver of 64 antenna elements is presented. It features instantaneous reception of the full Ku-band (2.05 GHz wide) in two orthogonal polarizations with wide scan angles by using time delay instead of phase shift. The receiver is part of a system for satellite broadcast TV reception on board of moving vehicles. Two SiGe radio frequency integrated circuits (RFICs) were developed, packaged in ceramic BGAs and assembled onto a 15-layer printed circuit board (PCB) which integrates the antenna elements. An outline of the system is given along with a detailed description. It sets a new standard in integration density. The receiver has extensive analog signal processing at intermediate frequency (IF)-level. A novel bipolar implementation for true time delay is proposed, with a continuous programmable delay range of 0…80 ps with less than 2.5 ps group-delay variation in 2 GHz bandwidth (BW). The wide BW calls for a constant group-delay implementation in the IF chain. The receiver (RFIC) consumes only 132 mW per channel. Each channel has 40 dB gain.

Shear strengths of CBGA/PBGA solder ball joints with lead-free solder pastes

The present study is carried out to characterise the ball shear strengths of ceramic ball grid array (CBGA) and plastic ball grid array (PBGA) packages with lead-free solder pastes. Three commercially available Sn/Ag/Cu (SAC) solder pastes such as Sn 96.5/Ag3.0/Cu0.5 and 95.5/Ag3.8/Cu0.7 with a no-clean flux are employed. The effects of temperature profiles during reflow on the strength of solder joints are studied. Their printing abilities are also observed. Of particular concern for ceramic ball grid array packages is the interaction between 90/10 Pb/Sn compound solder balls and SAC solder pastes. The composition of the solder paste region between the I/O pad and the solder ball is analysed using the energy dispersive X-ray (EDX) machine.

Norris–Landzberg Acceleration Factors and Goldmann Constants for SAC305 Lead-Free Electronics

Goldmann constants and Norris–Landzberg acceleration factors for SAC305 lead-free solders have been developed based on principal component regression models (PCR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Models have been developed in conjunction with stepwise regression methods for identification of the main effects. Package architectures studied include ball-grid array (BGA) packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermomechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermomechanical failure data. Data have been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature, and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Goldmann constants and the Norris–Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation datasets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experimental study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages (Lall et al., 2004, “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” Proceedings of the ITherm 2004, 9th Intersociety Conference on Thermal and Thermo-mechanical Phenomena, Las Vegas, Nevada, Jun. 1–4, pp. 259–267, Lall et al., 2005, “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” IEEE Trans. Compon. Packag. Technol., 28(3), pp. 457–466., flip-chip packages (Lall et al., 2005, “Decision-Support Models for Thermo-Mechanical Reliability of Leadfree Flip-Chip Electronics in Extreme Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, Orlando, FL, Jun. 1–3, pp. 127–136) and ceramic BGA packages (Lall et al., 2007, “Thermo-Mechanical Reliability Based Part Selection Models for Addressing Part Obsolescence in CBGA, CCGA, FLEXBGA, and Flip-Chip Packages,” ASME InterPACK Conference, Vancouver, British Columbia, Canada, Jul. 8–12, Paper No. IPACK2007-33832, pp. 1–18). The presented methodology is valuable in the development of fatigue damage constants for the application specific accelerated test datasets and provides a method to develop institutional learning based on prior accelerated test data.

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

Estimation of Curing Profile's Parameters for Flip Chip Packaging Using DSC and TGA

This paper presents the method to estimate curing profile's parameters for curing process of Moisture Resistance Cyanate Ester (MRCE) based underfill used in Flip Chip Ceramic Ball Grid Array (FC-CBGA). The two steps curing profile was found to eliminate voids formation in underfill during curing process. The important parameters in two steps curing profile such as first fixed temperature and duration of second temperature rise were estimated by superimposed of cure initiation curve and weight percentage loss curve of underfill epoxy material. Differential Scanning Calorimeter (DSC) analysis was carried out to characterize the cure kinetics reaction of underfill epoxy and produced the cure initiation curve. Thermal Gravimetric Analysis (TGA) was performed to characterize the weight loss of underfill and produced the weight loss curve. It was estimated that the first fixed temperature and duration of second temperature rise for two steps curing profile were 100 oC and 60-80 minutes respectively. The simulation experiment was conducted to verify the profile and no voids formation observed along this curing process.