Cellular Array Processor Research Articles

Convolutional kernel function algebra

Many systems for image manipulation, signal analysis, machine learning, and scientific computing make use of discrete convolutional filters that are known before computation begins. These contexts benefit from common sub-expression elimination to reduce the number of calculations required, both multiplications and additions. We present an algebra for describing convolutional kernels and filters at a sufficient level of abstraction to enable intuitive common sub-expression based optimizations through decomposing filters into smaller, repeated, kernels. This enables the creation of an enormous search space of potential implementations of filters via algebraic manipulation. We demonstrate how integral image and sliding window optimizations can be expressed in the context of common sub-expression elimination as well as show the direct use case for this algebra in massively SIMD multiply-free contexts such as in cellular processor arrays. We then show that this algebra is general enough to express and optimize kernels that use non-standard semi-rings to enable shortest path algorithms.

Thermodynamic cost of edge detection in artificial neural network (ANN)-based processors

ABSTRACT Architecture-based heat dissipation analyses allow us to reveal fundamental sources of inefficiency in a given processor and thereby provide us with road-maps to design less dissipative computing schemes independent of technology-base used to implement them. In this work, we study architectural-level contributions to energy dissipation in an Artificial Neural Network (ANN)-based processor that is trained to perform edge-detection task. We compare the training and information processing cost of ANN to that of conventional architectures and algorithms using 64-pixel binary image. Our results reveal the inherent efficiency advantages of an ANN network trained for specific tasks over general-purpose processors based on von Neumann architecture. We also compare the proposed performance improvements to that of Cellular Array Processors (CAPs) and illustrate the reduction in dissipation for special purpose processors. Lastly, we calculate the change in dissipation as a result of input data structure and show the effect of randomness on energetic cost of information processing. The results we obtained provide a basis for comparison for task-based fundamental energy efficiency analyses for a range of processors and therefore contribute to the study of architecture-level descriptions of processors and thermodynamic cost calculations based on physics of computation.

Low power high-performance smart camera system based on SCAMP vision sensor

Vision sensors based upon pixel-parallel cellular processor arrays offer the unique opportunity to realise high-performance, flexible, low power image processing systems. By virtue of processing on the focal-plane, the energy-demanding requirement to digitize a captured frame's raw pixel data is reduced, with returned data constituting only that which is salient. We describe a stand-alone vision system incorporating a SCAMP-3 vision chip, an FPGA and an ARM Cortex-M3 microcontroller. SCAMP integrated circuits operate as SIMD computers; each pixel incorporating a compact but powerful analogue processor and local memory, with all operations occurring in parallel over the 128x128 array. Algorithms are developed to operate natively upon the focal-plane as far as possible, with additional serial and higher-level operations occurring on the microcontroller. The power consumption of the system is algorithm-dependent. An algorithm developed for loiterer detection at 8fps has been shown to consume an average power of 5.5mW, with a more complex object tracking and counting system consuming 29mW.

Topographic implementation of particle filters on cellular processor arrays

Particle filters are a state-of-the-art method for the state estimation of non-linear stochastic systems. Recent many-core architectures and cellular processor arrays offer a new paradigm for algorithm development, which provides not only high performance, but also theoretical advances for parallel implementations. We have developed a new variant of the particle filter algorithm, which suits ideally implementation on a cellular processor array. The new algorithm often performs better than the classical one and a significant gain in running time can be achieved, especially when there is a large number of particles to be simulated.

Split and shift methodology on cellular processor arrays: area saving versus time penalty

ABSTRACTThis paper addresses the so‐called split and shift methodology. This methodology deals with the implementation of kernels of sizes that go above the physically implemented resources (local connections and weighting circuits) on synchronous cellular processor arrays (CPA), including the realization of large neighborhood operations and/or the reduction of the available hardware in order to drop the area consumption. Two main goals are pursued in the development of the methodology, namely: (1) minimum penalty at processing time and (2) absolutely no penalty at functional level. The paper presents different techniques and guidelines for the methodology application and introduces a Figure of Merit to evaluate them by relating area gains with time penalty. This, along with a kernel shape analysis, led us to propose more adequate configurations of weighting circuits and to justify the classical choice of North‐East‐West‐South connectivity. To validate the methodology, we realize several estimates over actual physical implementations, and we propose the realization over CPAs of the spin filters, scale invariant feature transform and speeded‐up robust features algorithms. A more in‐depth trade‐off analysis is realized over the implementation of the pixel level snakes algorithm. Copyright © 2012 John Wiley & Sons, Ltd.

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low-power consumption. An integrated circuit with proof-of-concept array of 24×60 cells has been fabricated in a 0.35µm three-metal CMOS process and tested. Occupying only 16×8µm2 the binary wave-propagation cell is designed to be used as a co-processor in general-purpose processor-per-pixel arrays intended for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 µm CMOS technology.

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on ite...

A Mixed-Mode Polynomial Cellular Array Processor Hardware Realization

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm/sup 2/, 1.027 million transistor cellular array processor with 2/spl times/72 PUs and 36 layers of memory in each was manufactured using a 0.25-/spl mu/m digital CMOS process. The array processor can perform gray scale Heun's integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72/spl times/72 data while keeping all input-output operations during processing local. One complete Heun's iteration round takes 166.4 /spl mu/s and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.

Signal processing by pulse‐driven molecular arrays

AbstractIn this paper cellular array processors composed of weakly Coulomb coupled molecules are studied. Equivalent circuits for molecules performing optically induced electron and proton transfer are presented, and pulse‐driven computing architectures are proposed. The polymer‐like molecular array is processing signals if it is subjected to a sequence of electromagnetic pulses of well‐defined frequency, envelope and length. Programming is accomplished by selecting proper sequence of pulses. Universality of the proposed architecture for computing is demonstrated. Copyright © 2003 John Wiley & Sons, Ltd.

Architecture and Design of 1-D Enhanced Cellular NeuralNetwork Processors for Signal Detection

One-dimensional cellular array processor architecture and design for neural-based partial response (PR) signal detection are presented. Analog parallel computing approaches have many attractive advantages in achieving low power, low cost, and faster processing speed by its uniquely coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorithm for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system performance evaluation. Analytical models and simulations on a design example of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2 µm CMOS technology. The processing rate can be beyond 1Gbps if it is implemented in the same amount of silicon area by using 0.5 µm CMOS technology. Such promising results clearly demonstrate the ability to meet the needs in future high speed data communication by VLSI realization of maximum likelihood sequence detectors based on the enhanced cellular neural network paradigm.

Behavioral simulation of densely-connected analog cellular array processors for high-performance computing

The analog cellular neural network (CNN) model is a powerful parallel processing paradigm in solving many scientific and engineering problems. The network consists of densely-connected analog computing cells. Various applications can be accomplished by changing the local interconnection strengths, which are also called coefficient templates. The behavioral simulator could help designers not only gain insight on the system operations, but also optimize the hardware-software co-design characteristics. An unique feature of this simulator is the hardware annealing capability which provides an efficient method of finding globally optimal solutions. This paper first gives an overview of the cellular network paradigm, and then discusses the nonlinear integration techniques and related partition issues, previous work on the simulator and our own simulation environment. Selective simulation results are also presented at the end.

Method and apparatus for recognizing unknown spoken words and by feature extraction and comparison with reference words

Speech recognition is performed in several successive phases, with each word being separated into elements of equal length. Each element is represented by a vector consisting of eight coefficients. After the end of a word is recognized, the word is successively compared with all reference words in a speech recognition apparatus. The recognition process is speeded up through the utilization of common hardware for all phases and by avoidance of idle time. A cellular array processor is used whose processing elements operated predominantly as filters in the feature extraction phase, and each element compares two vectors in the comparison phase. By gradual transitions between ends and beginnings of words, the capacities of all processors are equally utilized. The exchange of data is practically limited to an exchange between adjacent processors and is thus very efficient.

Parallel Computation of a Two-Dimensional Flow Field Using the MAC Methods.

This paper describes the basic issues in parallel computation of computational fluid dynamics (CFD) which are analyzed with a parallel computer. The parallel computer used is a cellular array processor called the AP 1000, operated by Fujitsu Parallel Computing Research Facilities. This paper is concerned with the adaptation of a Poisson equation solver, based on the successive over-relaxation method (SOR), to parallel computation. The convergence and relaxation factors of the SOR and the Red-Black SOR are examined. The optimum relaxation factor of the SOR decreases in the parallel computation ; while a high value of relaxation factor can be retained in the Red-Black SOR. Consequently, the Red-Black SOR is found to be a more effective solver in parallel computation. The present paper deals with parallel computation by means of the MAC. SMAC and HSMAC methods applied to a cavity flow. The computed field is decomposed into several domains. Each domain is assigned to one processor. With the methods tested, a high efficiency could be obtained by the present algorithms.

A real-time column array processor architecture for images

A column array processor (CAP) architecture for real-time (video rate) morphological image processing is proposed. The basic idea for this structure is that of a serial-to-parallel data input format and circular data stream processing. As compared to other structures, the column array processor appears to be more economical and flexible compared to a cellular array processor and more functional than a pipelined systolic array. The authors describe the concept and the structure of the processor and compare its operations to that of other processors. The primary motivation behind such an array processor is to implement morphological image analysis and processing algorithms in real-time for applications to video signals. Use of the processor is not limited to morphological operations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The 3-D Computer

The 3-D Computer is an implementation of a cellular array processor. Two technologies which make possible massive numbers of communication channels both between silicon wafers and through them have been developed. A parallel processor (single-instruction-multiple-data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D computer which has been built and operated is a small-scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32*32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this machine is >600 million operations per second with a 10-MHz clock, while the projected throughput of a full-scale machine is >100 billion operations per second, again with a 10-MHz clock. >

A Highly Parallel Processor CAP

AbstractThe aim of this study is to apply the unprecedented high‐speed computing made possible by parallel processing to a wide range of problems such as computer graphics. A highly parallel cellular array processor, the CAP‐256 has been developed in which 256 high‐performance processors, called cells, are connected together. The CAP‐256 includes a function by which a generated image is displayed in real‐time, as well as a function to construct various kinds of [inter‐processor] communication networks (topologies). A VLSI chip has been developed which integrates the communication and synchronization functions required for parallel processing, as well as the I/O function for the image. Using this VLSI chip, the cell was implemented in a compact form, and a small‐sized high‐performance parallel computer was implemented.To operate the cell, software called the cell OS (operating system) was developed. The software environment which has been implemented makes it possible to easily develop and efficiently execute application programs based on message communication. An image was generated using parallel ray‐tracing which has three to four times higher performance than that of the general‐purpose FACOM M‐380 mainframe computer. The authors are also attempting to develop applications for CAD problems such as automatic wiring as well as scientific calculations. The versatility of the CAR‐256 has been verified.

Cellular array processor CAP and applications

The general-purpose, highly parallel, cellular array processor (CAP) we developed features multiple-instruction stream, multiple-data stream (MIMD) processing and image display. Processor elements can number in several hundreds. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common bus interfaces for data broadcating and six 15M bit/s serial communication ports for local data communication. The chip also can process image data in real time for multiple processors. Use of the communication interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which ray tracing is used to generate quality images.

Two‐Dimensional Array Processor AAP2 and Its Programming Language

AbstractAn SIMD cellular array processor “AAP2” and its programming language AAPL have been developed. This array processor is packed into as little as 0.2 m volume in spite of its massive processor array being composed of 256 × 256 single‐bit processing elements [PEs], each of which has 8‐kbit local memory. The compact size is due to the simple and regular array structure for dense packing and a custom CMOS LSI with 8 × 8 PEs developed for the processor array.The massive processor array offers outstanding operation power together with the following functions: (1) modified SIMD control which is able to select a different operation function or different direction of inter‐PE transfer in each PE; (2) propagation transfer operation capable of propagating data through 15 PEs within one clock cycle (330 ns).The AAPL enables a simple and efficient program to be designed due to its APL‐like scanning statements and its primitive operation statements for unique AAP functions.The high performance of the AAP2 has been shown to be equivalent in simulation capability to the very high‐speed hardware logic simul.ator or routing capability of over 1000 MIPS in the automatic chip layout design.