Cell Delay Variation Research Articles

Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation

This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.

AN EFFECTIVE USAGE PARAMETER CONTROL MODEL FOR CELL POLICING IN ATM NETWORKS

The primary role of traffic control procedures is to protect the network so that it can achieve the required network performance objectives and yield a high quality of service (QoS). To guarantee the QoS, the network implements traffic control using the parameters agreed upon at the start of data transfer, thus avoiding problems with degraded QoS before they occur. This paper presents an efficient model for policing cells transmitted over ATM networks. The model was simulated by a program written in Java. From several simulation test runs and subsequent analysis, it can be deduced that the model gives a minimal cell transfer rate at a minimum intercell period, while the cell delay variation tolerance is held constant. Optimal cell loss ratio is also achieved when the minimum intercell period is held constant and the cell delay variation tolerance is high. The results show minimal cell loss ratio has been achieved and the data throughput of the model is high.

Performance analysis of data transmissions in MPLS and non-MPLS networks

Basic Network transactions specifies that datagram from source to destination is routed through numerous routers and paths depending on the available free and uncongested paths which results in the transmission route being too long, thus incurring greater delay, jitter, congestionand reduced throughput. One of the major problems of packet switched networks is the cell delay variation or jitter. This cell delay variation is due to the queuing delay depending on the applied loading conditions. The effect of delay, jitter accumulation due to the number of nodes along transmission routes and dropped packets adds further complexity to multimedia traffic because there is no guarantee that each traffic stream will be delivered according to its own jitter constraints therefore there is the need to analyze the effects of jitter. IP routers enable a single path for the transmission of all packets. On the other hand, Multi-Protocol LabelSwitching (MPLS) allows separation of packet forwarding and routing characteristics to enable packets to use the appropriate routes and also optimize and control the behavior of transmission paths. Thus correcting some of the shortfalls associated with IP routing. Therefore MPLS hasbeen utilized in the analysis for effective transmission through the various networks. This paper analyzes the effect of delay, congestion, interference, jitter and packet loss in the transmission of signals from source to destination. In effect the impact of link failures, repair paths in the variousphysical topologies namely bus, star, mesh and hybrid topologies are all analyzed based on standard network conditions.

Characterization of Standard Cells for Intra-Cell Mismatch Variations

With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variation (referred to as statistical characterization). Statistical characterization needs to be performed efficiently with acceptable accuracy as a function of several process and environmental parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and nonswitching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvement with acceptable accuracy, compared with Monte Carlo simulation. We show that this approach ensures an upper bound on the results while keeping the number of simulations for each cell independent of the number of devices.

Lens aberration aware placement for timing yield

Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due to their small extent. However, as process margins reduce, and as improvements in reticle enhancement techniques control variations due to other sources with increased efficacy, lens aberration-induced variations gain importance. For example, our experiments indicate that delays of most cells in the Artisan TSMC 90nm library are affected by 2--8% due to lens aberration. Aberration-induced variations are systematic and depend on the location in the lens field. In this article, we first propose an aberration-aware timing analysis flow that accounts for aberration-induced cell delay variations. We then propose an aberration-aware timing-driven analytical placement approach that utilizes the predictable slow and fast regions created on the chip due to aberration to improve cycle time. We study the dependence of our improvement on chip size, as well as use of the technique along with field blading which allows partial reticle exposure. We evaluate our technique on two testcases, AES and JPEG implemented in 90 nm technology. The proposed technique reduces cycle time by 4.322% (80ps) at the cost of 1.587% increase in trial-routed wirelength for AES. On JPEG, we observe a cycle time reduction of 5.182% (132ps) at the cost of 1.095% increase in trial-routed wirelength.

Novel DLC model for QoS enhancement of bursty VBR traffic in wireless ATM networks

AbstractSeveral data‐link control (DLC) protocol procedures have been proposed in order to provide reliable data transmission over powerless radio links. However, many quality of service (QoS) issues still need to be achieved such as balance between cell transfer delay (CTD) and cell loss rate (CLR), absence of cell delay variation (CDV) and network traffic utilisation. The main problem with wireless ATM is how to overcome the unreliability of the wireless link in order to maintain QoS requirements especially for variable bit rate (VBR) application. Here, we propose a model that provides QoS support for ATM virtual connections (VC) and solves the unreliability problem of the wireless ATM through an efficient DLC protocol for bursty VBR traffic. This model mainly concerns with enhancing QoS to gain error‐free wireless transmission and regulating VBR Traffic. Copyright © 2008 John Wiley & Sons, Ltd.

Adaptive CDV Compensation Algorithm for Satellite Networks

In this paper, we propose an adaptive compensation algorithm to compensate cell delay variation (CDV) occurring during ATM/TDMA transition in a satellite ATM network. The proposed CDV compensation algorithm uses two types of additional information: cell position information (Cp)indicating the number of cells (N) arriving within a control unit time (Tc) and positions of cells at a given time-and the number of cells in bursts-to take into account the characteristics of localized bursts. To evaluate the performance of the proposed algorithm, we performed a computer simulation based on an OPNET environment, using the Markov modulated Poisson process (MMPP) traffic model and assessed its effectiveness from varied standpoints. The results of the performance testing indicate that the proposed algorithm, while requiring significantly less additional information than previous CDV compensation algorithms, is able to more efficiently compensate CDV in localized burst traffic than the previous ones.

Performance of a new bus assignment algorithm for an ATM switch fabric

The measurement of the quality of service in ATM* networks involves the activation of the ATM layer management OAM functions. Once an ATM connection is set up, in-service performance monitoring based on OAM cells can be used to measure and estimate the ATM layer QoS parameters. In-service measurement of ATM layer QoS parameters such as cell delay variation, cell transfer delay, cell loss ratio, etc., is necessary to verify on one hand, if the network is meeting the requested QoS and on the other hand, if the users are receiving their promised QoS. Congestion conditions in ATM switches may cause gradual deteriorations in the quality of virtual paths or virtual channel connections in an ATM network. QoS measurement using OAM cells can accurately measure the overall quality of monitored ATM layer QoS parameters in order to detect such deteriorations before the service quality has dropped bellow an acceptable level. Several factors such as network load, congestion, bottlenecks, and incremenTS in network load may affect the cell delay variation of video transmissions in an ATM network. In this work, several ATM layer QoS parameters have been measured on a VBR video source using OAM cells. The simulation resulTS obtained show that with low network loads, the contribution of each individual ATM switch to the local and to the end-to-end CDV is not significant. In the presence of a bottleneck switch, the CDV presented by this switch becomes the dominant one at both local and end-to-end sides. When the network load is between 0.5 and 0.6, small incremenTS in network load do not alter the buffer performance of the non-congested ATM switches, and low values of CDV can be obtained. In contrast, it was found that there is a critical load between 0.65 and 0.7 where small incremenTS in network load may force the CDV to grow abruptly.

Asynchronous measurement of CDV in ATM networks using OAM cells

The synchronisation between source and destination clocks at network nodes to a common reference time of day is important in order to achieve accurate measurements of cells delays in ATM networks. Otherwise, direct measurement of the cell transfer delay and cell delay variation using time-stamped OAM cells would be inaccurate. In this work, a method for the accurate measurement of cell delay variation using OAM cells, which does not rely on synchronised clocks at the measurement points is presented. This is achieved by assuming that each ATM switch has the capability to process and to modify the information contained in the OAM cells. The system presented here was modelled by means of a block-oriented network simulator (BONeS), which is a graphically-oriented, general-purpose simulation language for modelling and simulating communications networks, including ATM networks. The measurements of the cell delay variation were carried out on a VBR video source generated by a real MPEG-2 encoder with a fixed quantizer step size. The simulation results obtained show that measurements of the cumulative cell delay variation carried out without synchronised clocks at the measurement points were very closed to those obtained using synchronised clocks at the measurement points.

Ethernet-PON을 위한 새로운 동적 대역 할당 알고리즘

광대역 액세스 망에서 합류, 분배 지점에서의 효율을 고려한 PON(Passive Optical Network)의 설계는 중요한 관심거리가 되고 있다. PON 구조는 매우 간단하지만, 가입자들에서 발생하는 상향 트래픽 제어를 위해서는 매체 접근 제어 프로토콜이 필요하다. 이러한 매체 접근 제어 프로토콜은 트래픽 클래스별 QoS(Quality of Service) 관리 기능, 효율적인 동적 대역 할당(Dynamic Bandwidth Assignment) 기능, CDV(Cell Delay Variation) 최소화 기능 등이 포함되어야 한다. 본 논문에서는 Ethernet-PON(EPON)을 사용하는 광대역 액세스 망에서 여러 트래픽 클래스를 지원하는 매체 접근 제어 프로토콜의 동적 대역 할당 안고리즘을 제시한다. 제안된 알고리즘의 성능 분석을 위해 MDRR 알고리즘과 성능을 비교, 분석하였고, 실험 결과 본 논문에서 제시한 Request-Counter 알고리즘이 보다 더 나은 서비스 품질을 보장받을 수 있음을 확인할 수 있었다. Earlier efforts on optical access concentrated on the design of PONs for the collection and distribution portion of the access network. The PON architecture is very simple but it requires a MAC protocol for control of upstream traffic. The MAC protocol must support QoS (Quality of Service) administration function by various traffic class, efficient dynamic bandwidth assignment function, CDV (Ceil Delay Variation) minimization function etc. This paper proposes a dynamic bandwidth assignment algorithm of the MAC protocol for a broadband access network using an Ethernet Passive Optical Network supporting various traffic class. We compare our proposed with MDRR algorithm using simulation, and confirmed that our proposed Request-Counter algorithm produces shorter average cell delay.

Fuzzy-based dynamic bandwidth allocation for heterogeneous sources in ATM networks

Abstract Asynchronous Transfer Mode (ATM)-based Broadband Integrated Services Digital Network (B-ISDN) is to support multiple classes of traffic with widely different characteristics and Quality of Service (QoS) requirements. A major challenge in this network is to guarantee the promised QoS for the admitted users, while maximizing the resource allocation through dynamic resource sharing. In the case of multimedia call, each of the substreams has its own distinct QoS requirements concerning Cell Loss Ratio (CLR), Cell Transfer Delay (CTD) and Cell Delay Variation (CDV). The ATM network attempts to deliver the required QoS by allocating appropriate resources (e.g. bandwidth, buffers), and bandwidth allocation is a key in achieving this. Dynamic bandwidth allocation polices reported so far in the literature deal with homogeneous sources only. They do not consider QoS parameters and lead to unequal queue growth. In this work, we present and analyze Fuzzy Logic (FL)-based dynamic bandwidth allocation algorithm for heterogeneous sources with multiple QoS (CLR, CTD, CDV, and the arrival rate) requirements. Here, each substream can declare a range of acceptable QoS levels (e.g. High, Medium, and Low). As QoS demand varies, the proposed algorithm allocates the best possible bandwidth to each of the substreams. This maximizes the utilization and fair distribution of resources. We validate the proposed allocation method in a variety of scenarios, and show that the required QoS can be obtained by appropriately tuning the Fuzzy Logic Controller (FLC).

Analysis of synchronization algorithms with time-out control over networks with exponentially symmetric delays

We study the performance of a class of time-offset estimation algorithms for synchronization of master-slave nodes based on asynchronous transfer of timing cells when GPS is not used. We implement a synchronization control mechanism based on cell acknowledgment time-out (TO) with wait or no wait options. We analyze the mechanism reliability and performance parameters over symmetric links using an exponential cell delay variation model. We show that the maximum-likelihood offset estimator does not exist for the exponential likelihood function. We analytically provide RMS error result comparisons for five ad hoc offset estimation algorithms: the median round delay, the minimum round delay, the minimum link delay (MnLD), the median phase, and the average phase. We show that the MnLD algorithm achieves the best accuracy over symmetric links without having to impose a strict TO control, which substantially speeds up the algorithm. We also discuss an open-loop estimation updating mechanism based on standard clock models.

A new per-VC scheduling scheme in ATM networks: two-phased weighted fair queuing

The asynchronous transfer mode networks should support widely different characteristics of services with different quality of service requirements, and should achieve a fair use of the available bandwidth. This paper proposes a new per-VC scheduling algorithm not only to improve the performance of cell loss probability (CLP) and cell delay variation (CDV) but also to maintain the fair utilization of available bandwidth. The two-phased weighted fair queuing (TWFQ) scheme makes use of the cell inter-arrival time of each connection for determining the cell service order among connections, which contributes to get a small CDV. To achieve low CLP, the TWFQ scheme allows the connections, which are suffering from more bursty input traffic, to send the cell in advance by using two scheduling phases. The simulation results show that TWFQ scheme provides better performance than SCFQ and WRR in terms of CDV and CLP, and also performs as well on the criteria of mean cell delay and bandwidth fairness as those schemes.

Partition equalizer: a scheduler for algorithm-agile-encryptor ATM networks

The ability of ATM Networks to support a wide range of applications has made it increasingly popular. As ATM Networks are more widely used, security services become a compelling requirement. Encryption in ATM Networks allows users to select an appropriate algorithm to implement security services for a given application. Algorithm-Agile-Encryptors (AAEs) implement multiple encryption algorithms in a single device. AAEs also reduce operational costs when they are shared among several users. However, algorithm agility may re-order cells belonging to different Virtual Circuits (VCs) and thereby affect the negotiated QoS. The two ways of scheduling the encrypted cells from the AAE are ‘FIFO queuing’ and ‘Delay equalization’. This paper addresses the effect of the existing scheduling schemes on the QoS of ATM Networks. Further, a scheduling scheme called Partition Equalizer (PE) has been proposed and analyzed. It has been shown that the PE reduces both the Cell Transfer Delay and the Cell Delay Variation compared to the other existing schemes such as ‘FIFO queuing’ and ‘Delay equalization’.

An efficient statistical multiplexing scheme for ATM real-time multimedia services

For VoD (video on demand) and the multimedia services in ATM (asynchronous transfer mode) networks, guaranteeing QoS (quality of service) for real-time traffic is emerging as an important issue. We present a novel multiplexing scheme to reduce the CDV (cell delay variation) and jitter in ATM multimedia traffic. We propose a two-stage statistical multiplexing scheme using a FIRO (first in random out) window and a state queue. The simulation results show that the CDV is significantly reduced due to reduced clumping and dispersing among VCs (virtual channels) in VPs (virtual paths).

Interdeparture time analysis of CBR traffic in AAL multiplexer with bursty background traffic

The authors present a discrete time model of a queue to represent an AAL multiplexer with two types of traffic and to analyse cell delay variation of constant bit rate (CBR) traffic in ATM networks. It is assumed that a single periodically deterministic CBR traffic stream and several variable size bursty background traffic streams are multiplexed in the AAL multiplexer and one ATM cell payload stream goes out. The AAL multiplexer is modelled as a BX + D/D/1 queue with all infinite buffer and the departure process of CBR cell payloads is analysed by using the queueing model with the superposed input traffic of CBR and bursty background streams. Both the packet and cell delay time distributons of the CBR traffic and the interdeparture time distribution of the CBR cells are obtained. The authors also give some numerical results for the performance measures.

Design and implementation of a QoS oriented data-link control protocol for CBR traffic in wireless ATM networks

This paper presents a QoS oriented Data Link Control (DLC) framework for transporting Constant Bit Rate (CBR) traffic over wireless ATM links. Data link control is usually omitted in fixed ATM networks because cell corruption due to channel error is extremely rare for reliable media like copper wire and optical fiber. However, for wireless, higher bit error rates are quite common due to shadowing and other fading effects. The purpose of DLC in wireless is to provide error-free transport to the higher layers by recovering corrupted cells at the link layer. A selective reject (SREJ) automatic repeat request (ARQ) based DLC protocol is used for CBR error recovery. For an ARQ based scheme, higher recovery rates can be achieved with larger cell transfer delay, caused by cell retransmissions. Since cell transfer delay and DLC recovery rate both translate to user-perceivable Quality-of-Service (QoS), it is important for the DLC to strike a balance between these two, depending on the application's requirements. To achieve this in our protocol, the retransmission procedure for a CBR cell is constrained to complete within a recovery time interval which is specified by the application at call-setup time. Also, a novel jitter removal scheme that reduces the cell delay variation caused by cell loss and retransmissions, is incorporated as a part of the DLC protocol. The proposed protocol is implemented on NEC's WATMnet prototype system. The implementation and its experimental results are reported for illustrating the performance and feasibility of the presented CBR DLC protocol. The experimental results show that the DLC protocol can be successfully applied for QoS-constrained error recovery of CBR traffic on a per-connection basis. These also indicate that the DLC can be programmed to attain a desirable tradeoff between cell transfer delay and cell recovery rate.

Fast convolution approximation scheme for estimatingend-to-end delay performance

A simple convolution approximation scheme is proposed to reduce the number of operations and the required amount of data in ATM networks. This approximation method can be used to estimate the end-to-end cell delay variation (CDV) using local information about cell delays in asynchronous transfer mode (ATM) networks.

Design of a multiple leaky buckets shaper

Asynchronous Transfer Mode (ATM) has been considered as the future trend for the information transfer in Broadband Integrated Services Digital Network (B-ISDN). ATM networks provide a guaranteed Quality of Service (QoS) for a variety of applications. One of the important QoS attributes is Cell Delay Variation (CDV). CDV measures how much delay variation will appear in cell transmission times. Call Admission Control (CAC) and Usage Parameter Control (UPC) are two main functions for achieving traffic control in ATM networks. The UPC scheme monitors and controls traffic in order to determine whether the established connections conform to the predefined parameters or not. For a real source operating at predefined parameters, some delay variation will occur in cell transmission times. CDV Tolerance (CDVT) controls the amount of acceptable deviation. Two classes of UPC methods have been proposed in the past to deal with CDV: one is to design an UPC method considering the worst traffic at User-Network Interface (UNI); the other is using a shaper for each connection of each link to accommodate CDV. In this paper, we propose a new shaper architecture to implement the UPC function that will eliminate CDV introduced between Terminal Equipment (TE) and the edge node of public networks. Our new shaper can follow multiple Generic Cell Rate Algorithm (GCRA) rules and consider all the traffic parameters. Furthermore, we use a simple method to reduce the memory requirement in the shaper. Insufficient memory might lead to incorrect cell departure in previous shapers. Simulation results show the performance is quite good and as expected.

Stream traffic management over an ATM passive optical network

Several alternatives based either on wired or wireless infrastructures are considered for the provision of broadband services in the local loop. In the field of wired solutions, Passive Optical Networks (PON) look very promising due to their bandwidth capacity. Also called APONs (ATM over PON), PON systems are designed in order to satisfy end-to-end ATM connections. Because it is based on a point-to-multipoint optical tree configuration, a PON access system requires a MAC protocol for the upstream traffic. Two approaches may be adopted for the design of an APON MAC protocol. The first approach considers a MAC protocol based on a work-conserving discipline combined with a stand-alone traffic shaper between the head of the optical tree and an ATM switch. The second approach consists in an integrated mechanism able to reduce Cell Delay Variation (CDV) of CBR/VBR connections by means of non-work conserving disciplines at the MAC layer. After having described the main characteristics of APON systems, we propose a new APON MAC protocol with integrated shaping well suited to real time traffic management. The performances of our protocol are investigated by means of both computer simulations and analytical modeling. By extension of our analytical study, a Call Admission Control procedure is proposed for real time VBR connections.