CDM Test Research Articles

Over-stress and under-stress effects in CDM testing

This paper describes two mechanisms that can lead to over-stress and/or under-stress when testing ICs for CDM robustness. We show that CDM testing of non-connected pins can result in over-stress or under-stress on the subsequently connected pin tested, and thus can lead to incorrect qualification. We also show that initial charge on the device before the actual stress can lead to higher or lower discharge current. Mitigation options for both phenomena are discussed. In addition, we show that in particular cases CDM stressing non-connected pins may identify unique fail modes.

Foreword for the Special Section on ESD CDM Tester, Modeling, and Characterization

The three invited papers in this special section are extensions of original works presented at the 2013 EOS/ESD Symposium.

EMMI Failure-Distributed Analysis of ESD Zapping and Protection Designs in Power VDMOS ICs

This paper deals with a detailed study of ESD failure modes, failures distribution and how to strengthen of the VDMOS ICs used for power applications. The ESD post-zapped failure of power VDMOS ICs due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. It is found that the ESD robustness is VESD(HBM) > VESD(MM) > VESD(CDM) for these non-ESD protected DUTs. Meanwhile, the ESD failure sites will be closed to the gate bonding pad as with a positive zapping and higher dV/dt pulse such as in CDM testing. And, the failure mappings have been studied to establish the difference in damaged features of HBM, MM, and CDM. Furthermore, the ESD protection designs of power VDMOS ICs are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

Pitfalls for CDM calibration procedures

A product qualification gave very different results for CDM testing between three labs. This paper describes the investigation into the root cause of these differences. The most relevant issues are the measurement bandwidth and the quality of the calibration modules. An improved procedure is proposed.

CDM tests on interface test chips for the verification of ESD protection concepts

The CDM failure threshold of microelectronic components are determined by the peak value of the discharge current. The requirements of the market, however, are given in terms of potential. In addition, it is not known how the CDM susceptibility of an IC is affected by its core circuitry. This paper introduces an idea how CDM protection concepts can be checked by tests on an interface test chip to guarantee satisfying product qualifications.

Capacitively coupled transmission line pulsing cc-TLP––a traceable and reproducible stress method in the CDM-domain

This paper describes a new test method called capacitively coupled transmission line pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance. The test results are compared with the ESD thresholds obtained by CDM tests. The cc-TLP results correlate well with the CDM data.

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, very-fast TLP tests, transient interferometric mapping, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.

Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

An electrostatic discharge (ESD) evaluation of a silicided 0.25 μm complementary metal-oxide-semiconductor (CMOS) technology is carried out by HBM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Dangerous parasitics of socketed CDM ESD testers

HBM, non-socketed and socketed CDM testing were performed on HF-ICs. By applying HBM and non-socketed CDM stress weak pins were located by selective stress. Socketed CDM, however, caused a damage at the weak pins, even when they were excluded from testing. Socketed and non-socketed CDM caused the same electrical failure signature. After insulating the weak pins from the tester circuitry, these pins survived the socketed CDM test without damage and the failure threshold increased. This behaviour is explained by the discharge of the parasitic tester capacitance through the weak pins, while other pins are tested.

ESD MONITOR CIRCUIT—A TOOL TO INVESTIGATE THE SUSCEPTIBILITY AND FAILURE MECHANISMS OF THE CHARGED DEVICE MODEL

ESD-monitor circuits are introduced and used to evaluate failure mechanisms and susceptibilities with respect to the charged device model. The performance of protection elements is studied by means of transmission line pulsing, electron beam probing and non-contact, non-socketed CDM tests. The capacitance connected to the source of the protection transistor and the resistance of this connection are critical. With respect to the circuitry and protection element, CDM-failure signatures of the monitor vary from an energy induced junction failure to a voltage induced gate oxide breakdown.

ESD MONITOR CIRCUIT—A TOOL TO INVESTIGATE THE SUSCEPTIBILITY AND FAILURE MECHANISMS OF THE CHARGED DEVICE MODEL

ESD-monitor circuits are introduced and used to evaluate failure mechanisms and susceptibilities with respect to the charged device model. The performance of protection elements is studied by means of transmission line pulsing, electron beam probing and non-contact, non-socketed CDM tests. The capacitance connected to the source of the protection transistor and the resistance of this connection are critical. With respect to the circuitry and protection element, CDM-failure signatures of the monitor vary from an energy induced junction failure to a voltage induced gate oxide breakdown.

ＣＤＭ試験による焼き菓子類の酸化安定性の評価

ＣＤＭ試験による焼き菓子類の酸化安定性の評価