Test circuits for fast and reliable assessment of CDM robustness of I/O stages

Abstract

CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, very-fast TLP tests, transient interferometric mapping, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures.