Abstract
This paper describes two mechanisms that can lead to over-stress and/or under-stress when testing ICs for CDM robustness. We show that CDM testing of non-connected pins can result in over-stress or under-stress on the subsequently connected pin tested, and thus can lead to incorrect qualification. We also show that initial charge on the device before the actual stress can lead to higher or lower discharge current. Mitigation options for both phenomena are discussed. In addition, we show that in particular cases CDM stressing non-connected pins may identify unique fail modes.
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