CD Uniformity Research Articles

Fundamental characterization of stochastic variation for improved single-expose extreme ultraviolet patterning at aggressive pitch

Background: With aggressive scaling of single-expose (SE) extreme ultraviolet (EUV) lithography to the sub-7-nm node, stochastic variations play a prominent role in defining the lithographic process window (PW). Fluctuations in photon shot noise, absorption, and subsequent chemical reactions can lead to stochastic failure, directly impacting electrical yield. Aim: Fundamental characterization of the mode and magnitude of these variations is required to define the threshold for failure. Approach: A complementary series of techniques is enlisted to probe the nature and modulation of stochastic variation in SE EUV patterning. Unbiased line edge roughness (LER), local critical dimension uniformity (LCDU), and defect inspection techniques are employed to monitor the frequency of stochastic variations leading to failures in line/space (L/S) and via patterning. Results: When characterizing different resists and illumination conditions, there is no change in unbiased LER or via LCDU with increasing critical dimension (CD). Stochastic defect density is correlated with CD for both L/S and via arrays, and there is a strong correlation with L/S electrical yield data. Conclusions: Traditional 3σ LER and via LCDU measurements are not sensitive enough to define and improve PW. For PW centering and yield improvement, stochastic defect inspection is a necessity.

Programmable pupil correction method for photolithography illumination system

The off-axis illumination (OAI) technology is one of the resolution enhancement technologies, and it used to reduce critical dimension (CD) and increase depth of focus (DOF) which are the important performance parameters of photolithography machine. The performance of illumination modes has great effect on critical dimension uniformity (CDU), H–V bias and overlay accuracy. In order that the pupil characteristic parameters can always meet the requirements for a long time using, it is necessary to adopt the pupil correction technology for photolithography illumination system. Using experiments and photolithography performance simulation, a programmable pupil correction method based on correction fingers is studied. The correction algorithm and its operation process are analyzed in detail. The experimental results show that the energy distribution of corrected pupils is more balanced than the uncorrected ones. Furthermore, the simulation results indicate that the corrected pupil could improve the exposure patterns in different aspects. The proposed method could determine the fingers’ position easily, and could directly reflect the pupil performance requirements.

Ultrathin initiated chemical vapor deposition polymer interfacial energy control for directed self-assembly hole-shrink applications

Integrated circuit layouts consist of patterned lines and holes, where holes define the electrical contacts between adjacent layers. Block copolymer directed self-assembly (DSA) successfully shrinks the critical dimension (CD) of these contacts beyond the resolution of conventional lithography. DSA also radically improves the CD uniformity. One particularly difficult step of the DSA hole-shrink process involves establishing the correct interfacial energy throughout a lithographically templated hole to ensure good assembly. Initiated chemical vapor deposition (iCVD) is a uniform, ultrathin, ultraconformal, all-organic deposition technique that allows for precise control of the interfacial energy. In this work, the authors use iCVD of polydivinylbenzene at film thicknesses below 5 nm to blend the interfacial energy of the coated film with that of the silicon/spin-on carbon template. They fully characterize the iCVD surface by means of two liquid surface energy measurements. They further identify the interfacial energies presented by these functionalized templates through qualitative hole-island tests as well as quantitative harmonic mean estimations. In parallel, the authors run theoretically informed coarse grained simulations with the determined interaction parameters and DSA experiments and find good agreement across the range of chemistries created. Through careful control of iCVD conditions, especially filament temperature, they achieve a strong polystyrene-preferential sidewall with a nonpreferential bottom which they then demonstrate, both in the simulation and in the experiment, allows for a successful hole-shrink process across a wide range of template hole diameters.

Thermal modelling and design of dynamically-controlled heater plates for high temperature processing of 300 mm wafers

The temperature uniformity of heater plates (HPs) should be sustained due to critical dimension uniformity and robust operation in high temperature processing of 300 mm wafers. It is very challenging to maintain the temperature uniformity of the HP despite the dynamic control of power inputs and temperatures. The packaged power terminals (PPTs) of the HPs may considerably affect their thermal reliability. Hence, the sophisticated thermal modellings and designs of the HPs and the PPTs are necessary. In this study, the finite element analysis (FEA) thermal models of the HP and the PPT were generated, experimentally validated, and employed for the analysis and the design. The influences of the heating element width, the heating element gap, and the zone gap on the thermal performance of the HP were investigated. The parametric influences of the substrate thickness on the thermal performance of the PPT were also explored. The results show that the effect of the heating element width on the temperature of the HP is almost negligible. The results have found that a sophisticated design of the heating elements may reduce the radial temperature difference of the HP by 56 % compared with the baseline case. The results suggest that the sophisticated design may enable both the simplified structure and the enhanced temperature uniformity of the HP.

Wafer CD Uniformity Improvement in Negative Tone Development Process

WCDU (wafer critical dimension uniformity) has become one of the most momentous factors in the resist process for mass production. Non-uniform WCDU, CD value changes from wafer center to edge, can occur in resist process despite tight critical dimension uniformity (CDU). In this paper, the resist components and the resist process conditions that influence on WCDU variation in negative tone development (NTD) process will be discussed. WCDU was measured with various parameters to understand the causes of current performance.

55‐2: Essential Mask Quality for High‐End Resolution Displays

This paper proposes a best practice to produce the photomasks with the state‐of‐the‐art quality, suitable for high resolution panel patterning. In order to extend the panel patterning process capability, high CD performance (Resolution, CD MTT and CD Uniformity) of photomask is essential and RET(Resolution Enhancement Technology) such as PSM, OPC and OAI will be prominent technology for mask business. PSM and OPC technology on RET will be new challenges for future high resolution panel. These challenges require new generation photomask writer, PSM manufacturing capability.

Stochastic printing failures in extreme ultraviolet lithography

Stochastic effects in lithography are known to be the cause of critical dimension (CD) variability, quantified, e.g., by linewidth roughness or local CD uniformity, but—when the CDs are small—they can also lead to printing failures, and hence have a significant impact on yield. We will focus on these printing failures and review three important topics in this relatively new field. First, we will look at how these failures can be detected and show how either CD-SEM, e-beam inspection, and optical defect inspection can play a useful role. Next, we consider the important question of how the stochastic failure probability (which we quantify by a metric we call “Not OK,” abbreviated NOK) depends on the lithography- and process-settings, a question that is of obvious importance when looking for conditions that will minimize the failure probability and hence maximize the yield. Finally, we will discuss to what extent we can fit experimentally observed failure probabilities, to empirical models. Such models can play a vital role in future OPC-verification flows, where screening full mask layouts for “stochastic hot spots” is expected to become a mandatory step.

EUV vote-taking lithography for mitigation of printing mask defects, CDU improvement, and stochastic failure reduction

Vote-taking lithography is a method for mitigating mask defects, which has been applied in the 1980s to enhance yield. Vote-taking sums up N different mask images with identical content, each at 1 / N dose, to mitigate the defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N − 1 masks. Vote-taking has recently been reconsidered for extreme ultraviolet (EUV) lithography, where it might provide a temporary solution for situations in which the defectivity conditions are not yet meeting expectations. This paper provides a thorough experimental assessment of the implementation of vote-taking and discusses its pro’s and con’s. Based on N = 4 vote-taking, we demonstrate the capability to mitigate different types of mask defects. We found additional benefits of blending different mask images, distinct from mask defect reduction. Experimental results will be shown that demonstrate improved critical dimension uniformity (CDU), both local CDU and intrafield CDU, reduced overlay errors, and smaller stochastic defect levels. Finally, we perform dedicated throughput calculations based on the qualification performance of ASML’s NXE:3400B scanner. This work must be seen in the light of an open-minded search for options to optimally enable and implement EUV lithography. Although defect-free masks and EUV pellicles are without argument essential for most of the applications, we investigate whether some applications could benefit from vote-taking.

Assessment of pattern variability and defectivity by large-scale SEM metrology with >100 million measurements

We present an experimental study of pattern variability and defectivity, based on a large data set with >112 million critical dimension (CD) and via area measurements from a Hermes Microvision Inc. (HMI) high-throughput e-beam tool. The test case is a 10-nm node static random-access memory via array patterned with a deep ultraviolet immersion litho-etch-litho-etch process, where we see a variation in mean size and litho sensitivities between different unique via patterns that leads to significant differences in defectivity. The large data volume made available by high-throughput inspection capability of the HMI eP5 tool enables analysis to reliably distinguish global and local CD uniformity variations, including a breakdown into local systematics and stochastics. From a closer inspection of the tail end of the distributions and estimation of defect probabilities, we conclude that there is a common defect mechanism and defect threshold despite the observed differences of specific pattern characteristics. In addition, we studied wafer fingerprints for both global CD uniformity (GCDU) and local CD uniformity (LCDU), including stochastics. We used LCDU and GCDU wafer maps to identify correlations between those parameters and defect count. We expect that the analysis methodology presented can be applied for defect probability modeling as well as general process qualification in the future.

Measurement of pattern roughness and local size variation using CD-SEM

Measurement of line edge roughness (LER) is discussed from four aspects: edge detection, power spectrum densities (PSD) prediction, sampling strategy, and noise mitigation. General guidelines and practical solutions for LER measurement today are introduced. Advanced edge detection algorithms such as the wave-matching method are shown to be effective for robustly detecting edges from low SNR images, whereas a conventional algorithm with weak filtering is still effective in suppressing SEM noise and aliasing. An advanced PSD prediction method such as the multitaper method is effective in suppressing sampling noise within a line edge to analyze, whereas a number of lines are still required for suppressing line-to-line variation. Two types of SEM noise mitigation methods, such as the “apparent noise floor” subtraction method and LER-noise decomposition using regression analysis, are verified to successfully mitigate SEM noise from PSD curves. These results are extended to local critical-dimension uniformity (LCDU) measurement to clarify the impact of SEM noise and sampling noise on LCDU.

Stochastics in extreme ultraviolet lithography: investigating the role of microscopic resist properties for metal-oxide-based resists

Due to the high energy of extreme ultraviolet (EUV) photons, stochastic effects become more important at a constant dose when compared with deep ultraviolet exposures. Photoresists are used to transfer information from the aerial image into physical features and play an important role in the transduction of these stochastic effects. Recently, metal-oxide-based nonchemically amplified resists (non-CARs) have attracted a lot of attention. We study how the properties of these non-CARs impact the local critical dimension uniformity (LCDU) of a regular contact hole array printed with EUV lithography using Monte Carlo simulations and an analytical model. We benchmark both the simulations and the analytical model to experimental data, and then use the flexibility of both methods to systematically investigate the role of microscopic resist properties in the final LCDU. It is found that metal-oxide clusters should be <1 nm in diameter, otherwise granularity will have a significant contribution to LCDU. When varying resist properties to change the resist dose-to-size, we find that the LCDU scaling with dose depends on how the resist is modified. After performing an overall sensitivity analysis to identify the optimum scaling of LCDU with dose, we find a scaling of dose − 0.5 when the development threshold is modified, and a scaling of dose − 0.33 when core radius or the quantum efficiency is changed.

Deep UV Lithography Process in Generic InP Integration for Arrayed Waveguide Gratings

Low-excess-loss arrayed waveguide gratings are enabled by unique application of deep UV lithography in InP integrated photonics through reduced feature sizes and, more specifically, well-resolved inter-waveguide gap dimensions. Submicrometer wafer-flatness is shown to be required to achieve the critical dimension uniformity better than 10 nm on 3-in substrates. Arrayed waveguide grating devices were fabricated and the effect of inter-waveguide gap scaling on the excess losses was measured and compared to simulations. Excess losses down to 0.15 dB were demonstrated to be lower than predicted with the 2-D simulations. The tapering of the etch depth inside the gaps due to the lag effect of the etch process may explain the improvements.

35.4: UV LED ILLUMINATION STEPPER OFFERS HIGH PERFORMANCE AND LOW COST OF OWNERSHIP

Flat panel displays (FPD) are electronic viewing technologies used to let people see content in media and entertainment, consumer electronics, personal computer and mobile devices. Other applications and industries are medical, transportation and industrial equipment. FPD is often the preferred choice due to lower weight and less power consumption. Common types of FPD are liquid crystal display (LCD), plasma display panels (PDP) and organic light‐emitting diode (OLED).The global market for FPD continues to grow due to the high demand in the automobile and smartphone industries. As a result of the high demand, the FPD manufacturing industry continues to remain highly competitive. In this cost sensitive arena, FPD manufacturers need to find new ways to reduce the cost of ownership of lithography equipment.Most lithography systems in FPD manufacturing plants use high power mercury ARC lamps to generate i‐line (365nm) wavelength for the photoresist exposure process. This is a costly process as the mercury ARC lamps have a limited lifetime, typically less than one month, which results in downtime to swap lamps.. The cost of replacing the high power mercury ARC lamp, together with the high electricity consumption, and disposal of mercury waste, turns out to be a substantial operating cost.This paper will demonstrate how the use of ultraviolet light emitting diode (UV LED), in replacing the high power mercury lamp, will reduce the overall operating cost which therefore lowers the cost of ownership of the stepper. The breakdown of cost structure will be discussed in detail and show that UV LED is a good replacement solution for the high power mercury ARC lamp.The throughput improvement by using UV LED will also be discussed and compared to the conventional high power mercury arc lamp. The analysis will also show that the consistency of throughput, as compared to the degradation of mercury arc lamp intensity, as well as the time saved for replacement further reduces operating costs.This paper also demonstrates the improved performance of dose accuracy and repeatability, as well as the capability to achieve extremely low exposure doses without compromising dose accuracy. The improvement in stepper reliability by removing the conventional shutter moving parts will also be discussed.The performance data for illumination intensity, dose accuracy, uniformity, spectral line width, CD uniformity and cost reduction will be discussed in detail. The final analysis will show that moving to UV LED illumination offers lower cost and better performance.

Consequences of atomic layer etching on wafer scale uniformity in inductively coupled plasmas

Atomic layer etching (ALE) typically divides the etching process into two self-limited reactions. One reaction passivates a single layer of material while the second preferentially removes the passivated layer. As such, under ideal conditions the wafer scale uniformity of ALE should be independent of the uniformity of the reactant fluxes onto the wafers, provided all surface reactions are saturated. The passivation and etch steps should individually asymptotically saturate after a characteristic fluence of reactants has been delivered to each site. In this paper, results from a computational investigation are discussed regarding the uniformity of ALE of Si in Cl2 containing inductively coupled plasmas when the reactant fluxes are both non-uniform and non-ideal. In the parameter space investigated for inductively coupled plasmas, the local etch rate for continuous processing was proportional to the ion flux. When operated with saturated conditions (that is, both ALE steps are allowed to self-terminate), the ALE process is less sensitive to non-uniformities in the incoming ion flux than continuous etching. Operating ALE in a sub-saturation regime resulted in less uniform etching. It was also found that ALE processing with saturated steps requires a larger total ion fluence than continuous etching to achieve the same etch depth. This condition may result in increased resist erosion and/or damage to stopping layers using ALE. While these results demonstrate that ALE provides increased etch depth uniformity, they do not show an improved critical dimension uniformity in all cases. These possible limitations to ALE processing, as well as increased processing time, will be part of the process optimization that includes the benefits of atomic resolution and improved uniformity.

An embedded neutral layer for advanced surface affinity control in grapho-epitaxy directed self-assembly.

Advanced surface affinity control for grapho-epitaxy directed self-assembly (DSA) patterning is essential for providing reliable DSA-based solutions for the development of semiconductor patterning. Independent control of surface affinity between the bottom and the sidewalls of a topographical guiding structure was achieved by embedding an ultrathin layer in the guiding template stack. The implementation of an embedded layer with tunable surface properties for DSA grapho-epitaxy was evaluated and optimized on 300 mm wafers by critical dimension SEM characterization. It was demonstrated that a thin protective layer, placed between the hard mask guiding template and the embedded layer, allows the preservation of the surface properties of the embedded layer during guiding template etching. The DSA performances of this novel grapho-epitaxy integration, using a topographical template patterned with 193 nm immersion lithography, were evaluated by monitoring the success rate and the critical dimension uniformity of the shrunk contacts. FIB-STEM analyses were further carried out to analyze the residual polymer thickness on the resulting contacts. This new integration leads to the control of the polymer residual thickness (a few nanometers) and uniformity (inferior to 1 nm) at the bottom of the guiding template which will facilitate the subsequent DSA pattern transfer.

Stochastic effects in EUV lithography: random, local CD variability, and printing failures

Stochastic effects in lithography are usually quantified through local CD variability metrics, such as line-width roughness or local CD uniformity (LCDU), and these quantities have been measured and studied intensively, both in EUV and optical lithography. Next to the CD-variability, stochastic effects can also give rise to local, random printing failures, such as missing contacts or microbridges in spaces. When these occur, there often is no (reliable) CD to be measured locally, and then such failures cannot be quantified with the usual CD-measuring techniques. We have developed algorithms to detect such stochastic printing failures in regular line/space (L/S) or contact- or dot-arrays from SEM images, leading to a stochastic failure metric that we call NOK (not OK), which we consider a complementary metric to the CD-variability metrics. This paper will show how both types of metrics can be used to experimentally quantify dependencies of stochastic effects to, e.g., CD, pitch, resist, exposure dose, etc. As it is also important to be able to predict upfront (in the OPC verification stage of a production-mask tape-out) whether certain structures in the layout are likely to have a high sensitivity to stochastic effects, we look into the feasibility of constructing simple predictors, for both stochastic CD-variability and printing failure, that can be calibrated for the process and exposure conditions used and integrated into the standard OPC verification flow. Finally, we briefly discuss the options to reduce stochastic variability and failure, considering the entire patterning ecosystem.

The Improvement of the Pattern Wiggling Profile by Photo Resist Treatment

For advanced node such as 14nm technology and beyond, Patterning is one of the key challenges in the semiconductor industry. Advanced pattern transfer techniques such as negative tone development (NTD) technology are under investigation to enable the aggressive pitch requirements demanded. Even though, just as traditional positive tone development (PTD) technique, a pattern wiggling issue has arisen with the reduction of pattern dimension during dry etch process, which prevents the successful pattern transfer [1]. Two kinds of wiggling solutions have been proposed. One is the lithographic resolution such as changing the physical properties of the under-layer materials [2-4]. The other is the gases treatment in the tri-layer process such as H2plasma for spin-on carbon (SOC) hard-mask [5] and HBr and Ar plasma treatment for photoresist [6]. However, with the decrease of device size, a single method hardly eliminates wiggling and meets the pattern target. Besides, the requirements for Line Edge Roughness (LER)/Line Width Roughness (LWR); critical dimension uniformity (CDU); through pitch are extremely aggressive in advanced technology. Therefore, the characteristics of the dry etching process play an increasingly import role in defining the outcome of the pattern process. In this paper, we will demonstrate the method of PR treatment (both PTD and NTD techniques) that improves LER/LWR for trench pattern in dry etch ICP etcher. Meanwhile, the difference of PR treatment methods between PTD and NTD is illuminated. What’s more, in PR treatment methods, other pattern behavers such as CD, CD uniformity, through pitch are concerned during improving LER/LWR process, and aim to get a good result of all aspects. At last, the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR are studied. Acknowledgement REFERENCES [1] Goji Wakamatsu, Kentaro Goto, Yoshi Hishiro, Taiichi Furukawa al., Advances in Resist Materials and Processing Technology XXIX, Proc. of SPIE Vol. 8325 83250T-1,(2012) [2] Makoto, M., Mitsuaki, I., Takashi, K., Hisashi, H, and Seiji, F., Proc. SPIE7972,797226 (2011). [3] Tadokoro M., Yonekura K., Yoshikawa K., Ono Y., Ishibashi T., Hanawa T., Fukiwara N., Matsunobe T., MatsudaK., J. Vac. Sci.Technol. B,26, 67-71 (2008). [4] Someya, Y., Shinjo, T., Hashimoto, K., Nishimaki, H., Karasawa, R., Sakamoto, R., Matsumoto,T., Proceedings of the SPIE, vol.8325, 83250U (2012). [5] M. Tadokoro, K. Yonekura, K. Yoshikawa, Y. Ono, T. Ishibashi,T. Hanawa, and N. Fujiwara, J. Vac. Sci. Technol. B 26 (1) Jan/Feb( 2008) [6] E. Pargon, K. Menguelti, M. Martin, A. Bazin, O. Chaix-Pluchery, C. Sourd, S. Derrough, T. Lill, and O. Joubert, Journal of Applied Physics 105, 094902 (2009)

The Improvement of the Pattern Wiggling Profile by Photo Resist Treatment

For advanced node such as 14nm technology and beyond, Patterning is one of the key challenges in the semiconductor industry. Advanced pattern transfer techniques such as negative tone development (NTD) technology are under investigation to enable the aggressive pitch requirements demanded. Even though, just as traditional positive tone development (PTD) technique, a pattern wiggling issue has arisen with the reduction of pattern dimension during dry etch process, which prevents the successful pattern transfer. Two kinds of wiggling solutions have been proposed. One is the lithographic solution. The other is the gases treatment in the tri-layer process. However, with the decrease of device size, a single method hardly eliminates wiggling and meets the pattern target. Besides, the requirements for Line Edge Roughness (LER)/Line Width Roughness (LWR); critical dimension uniformity (CDU); through pitch are extremely aggressive in advanced technology. Therefore, the characteristics of the dry etching process play an increasingly import role in defining the outcome of the pattern process. In this paper, we demonstrate the method of PR treatment (NTD techniques) that improves LER/LWR for trench pattern in dry etch CCP etcher. Meanwhile, the difference of PR treatment methods between traditional and special treatment is illuminated. What’s more, in PR treatment methods, other pattern behavers such as CD, through pitch are concerned during improving LER/LWR process, and aim to get a good result of all aspects. At last, the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR are studied.

Challenges of anamorphic high-NA lithography and mask making

Abstract Chip makers are actively working on the adoption of 0.33 numerical aperture (NA) EUV scanners for the 7-nm and 5-nm nodes (B. Turko, S. L. Carson, A. Lio, T. Liang, M. Phillips, et al., in ‘Proc. SPIE9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 977602 (2016) doi: 10.1117/12.2225014; A. Lio, in ‘Proc. SPIE9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 97760V (2016) doi: 10.1117/12.2225017). In the meantime, leading foundries and integrated device manufacturers are starting to investigate patterning options beyond the 5-nm node (O. Wood, S. Raghunathan, P. Mangat, V. Philipsen, V. Luong, et al., in ‘Proc. SPIE. 9422, Extreme Ultraviolet (EUV) Lithography VI’, vol. 94220I (2015) doi: 10.1117/12.2085022). To minimize the cost and process complexity of multiple patterning beyond the 5-nm node, EUV high-NA single-exposure patterning is a preferred method over EUV double patterning (O. Wood, S. Raghunathan, P. Mangat, V. Philipsen, V. Luong, et al., in ‘Proc. SPIE. 9422, Extreme Ultraviolet (EUV) Lithography VI’, vol. 94220I (2015) doi: 10.1117/12.2085022; J. van Schoot, K. van Ingen Schenau, G. Bottiglieri, K. Troost, J. Zimmerman, et al., ‘Proc. SPIE. 9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 97761I (2016) doi: 10.1117/12.2220150). The EUV high-NA scanner equipped with a projection lens of 0.55 NA is designed to support resolutions below 10 nm. The high-NA system is beneficial for enhancing resolution, minimizing mask proximity correction bias, improving normalized image log slope (NILS), and controlling CD uniformity (CDU). However, increasing NA from 0.33 to 0.55 reduces the depth of focus (DOF) significantly. Therefore, the source mask optimization (SMO) with sub-resolution assist features (SRAFs) are needed to increase DOF to meet the demanding full chip process control requirements (S. Hsu, R. Howell, J. Jia, H.-Y. Liu, K. Gronlund, et al., EUV ‘Proc. SPIE9048, Extreme Ultraviolet (EUV) Lithography VI’, (2015) doi: 10.1117/12.2086074). To ensure no assist feature printing, the assist feature sizes need to be scaled with λ/NA. The extremely small SRAF width (below 25 nm on the reticle) is difficult to fabricate across the full reticle. In this paper, we introduce an innovative ‘attenuated SRAF’ to improve SRAF manufacturability and still maintain the process window benefit. A new mask fabrication process is proposed to use existing mask-making capability to manufacture the attenuated SRAFs. The high-NA EUV system utilizes anamorphic reduction; 4× in the horizontal (slit) direction and 8× in the vertical (scanning) direction (J. van Schoot, K. van Ingen Schenau, G. Bottiglieri, K. Troost, J. Zimmerman, et al., ‘Proc. SPIE. 9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 97761I (2016) doi: 10.1117/12.2220150; B. Kneer, S. Migura, W. Kaiser, J. T. Neumann, J. van Schoot, in ‘Proc. SPIE9422, Extreme Ultraviolet (EUV) Lithography VI’, vol. 94221G (2015) doi: 10.1117/12.2175488). For an anamorphic system, the magnification has an angular dependency, and thus, familiar mask specifications such as mask error factor (MEF) need to be redefined. Similarly, mask-manufacturing rule check (MRC) needs to consider feature orientation.

A full-process chain assessment for nanoimprint technology on 200-mm industrial platform

Abstract To evaluate the maturity of the wafer-scale NanoImprint lithography (NIL) process, laboratory of electronic and communication technology (LETI) and EV Group (EVG) launched the Imprint Nanopatterning Solution Platform for Industrial Assessment program (INSPIRE), which aims at building a nanoimprint solution platform for industrial assessment and provide a unique open ecosystem for the standardization of the nanoimprint process. This program enabled to gather EVG know-how for the tool manufacturing and its long expertise in bonding activities, and the established methods and advanced microelectronic environment. Presented as an upstream phase, metrology and defectivity were performed on dedicated assessment designs to address critical dimension uniformity (CDU) at wafer scale for a large number of imprints, defectivity on imprints and masters, and alignment capabilities of the nanoimprint HERCULES® platform of EVG. We demonstrate that the critical points are the anti-sticking layer for the defectivity, the CD shrinkage for the CDU, and the stiffness of the soft stamp for the overlay uniformity. Thus, we bring to light the actual capabilities of the HERCULES® platform, and open the discussions on the opportunities for this technology with the possible improvements for the process.