Cascode Topology Research Articles

A Transformer Feedback <inline-formula> <tex-math notation="LaTeX">${G}_{m}$ </tex-math> </inline-formula>-Boosting Technique for Gain Improvement and Noise Reduction in mm-Wave Cascode LNAs

This paper presents the analysis and design of a novel topology of a low-noise amplifier (LNA) with gain improvement and noise reduction simultaneously. A transformer feedback ${ g}_{ m}$ -boosting technique is proposed in a single-ended cascode topology to increase the gain and reduce the noise. The proposed technique is theoretically formulated and detailed analyses are presented. Two V-band single-ended cascode LNAs, with a transformer and transmission line for impedance matching, respectively, are demonstrated to verify this technique. Fabricated in a 65-nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best NF and power gain among all the published V-band LNAs in 65-nm CMOS up to date. The transmission-line-based (TL-based) LNA exhibits a minimum NF of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement. Both the LNAs consume 18 mA from a power supply of 1.1 V.

An 88.5–110 GHz CMOS Low-Noise Amplifier for Millimeter-Wave Imaging Applications

This letter presents a wideband millimeter-wave low-noise amplifier (LNA) in a 65 nm CMOS technology. The amplifier adopts five-stage cascode topology with L-type input matching and T-type output matching. By distributing the peak gains of first four stages at two frequency points, the LNA achieves a flat gain response over a wide bandwidth. The measurement results show that the amplifier features a peak gain of 16.7 dB at 104 GHz, a minimum NF of 7.2 dB, and a 3 dB bandwidth of 21.5 GHz. The LNA consumes 48.6 mW and occupies a compact core area of 0.05 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A self-control technique for high efficiency class-E CMOS power amplifier

In this paper, a self-control (SC) technique for high efficiency class-E CMOS power amplifier is presented for GSM standard. Cascode topology due to high sustainability of voltage stress is mostly considered in CMOS PAs, but slow transition of common-gate device from triode to cut-off region is the most problematic issue of cascode configuration and the main source of power loss. In order to minimize its power loss a positive feedback technique is used. The proposed technique speeds up on-to-off and off-to-on transition time and lower the on and off drain׳s voltage of the common-gate device. Therefore, the common-gate device turns off and on instantly after common-source device in lower drain voltage and consequently the technique shows an improvement in the overall performance of the PA. To demonstrate its performance a self-control class-E CMOS PA has been designed, simulate, and compared to conventional class-E CMOS PA. It has shown that more than 2% improvement is achieved in power-added efficiency (PAE). Under a 3.3V power supply, the proposed CMOS PA in 0.18um CMOS process at 1.8GHz gives 29.6dBm output power.

Design investigation to improve voltage swing and bandwidth of the SiGe driver circuit for a silicon electro-optic ring modulator

Abstract. This paper reports on a new SiGe driver IC to address the low breakdown voltage level of modern BiCMOS transistors. An optical modulator driver IC in SiGe 250 nm technology with a supply voltage of 4.5 V is presented. This driver IC consists of pre- and main driver stages where a newly modified cascode topology and capacitance degeneration technique is employed to meet current application requirements; high voltage swing at high datarate. The simulation results show a differential output voltage swing of 3.9 Vp-p at 14 Gbps data rate, according to the FDR Infiniband standard.

A Class-E Tuned W-Band SiGe Power Amplifier With 40.4% Power-Added Efficiency at 93 GHz

A W-band power amplifier with Class-E tuning in a 0.13 $\mu{\rm m}$ SiGe BiCMOS technology is presented. Voltage swing beyond $BV_{\rm CBO}$ is enabled by the cascode topology, low upper base resistance, and minimally overlapping current-voltage waveforms. At 93 GHz with 4.0 V bias, the peak power-added efficiency and saturated output power are measured to be 40.4% and 17.7 dBm, respectively. With the bias increased to 5.2 V, the peak power-added efficiency and saturated output power at 93 GHz are measured to be 37.6% and 19.3 dBm, respectively.

Improved T-Shaped Gate Double Heterojunction AlGaN/GaN/InGaN/GaN HEMT-Based Wideband Flat LNA

ABSTRACTIn this paper, we report and design a new kind of AlGaN/GaN/InGaN/GaN high electron mobility transistor (HEMT), consisting of T-shaped gate with low resistance contacts, and the performance of a cascode topology low noise amplifier (LNA) with shunt-feedback technique for wideband and flat gain, based on mentioned HEMT. The proposed LNA has ∼17.5 dB of gain from 3 to 10 GHz with a noise figure of 0.7–1.1 dB in the band of interest. The direct current (DC) and radio frequency advantages of the reported HEMT and the superior flat gain performance of the cascode LNA are demonstrated.

Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65- and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of $-{\hbox{44.5 dB}}$ . With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of $-{\hbox{44.5 dB}}$ . The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power.

J-band amplifier design using gain-enhanced cascodes in 0.13 μm SiGe

This paper presents two J-band amplifiers in different 0.13 μm SiGe technologies: a small signal amplifier (SSA) in a technology in which never before gain has been shown over 200 GHz; and a low noise amplifier (LNA) design for 230 GHz applications in an advanced SiGe HBT technology with higher fT/fmax, demonstrating the combination of high gain, low noise, and low power in a single amplifier. Both circuits consist of a four-stage pseudo-differential cascode topology. By employing series–series feedback at the single-stage level the small-signal gain is increased, enabling circuit operation at high-frequencies and with improved efficiency, while maintaining unconditional stability. The SSA was fabricated in a SiGe BiCMOS technology by Infineon with fT/fmax values of 250/360 GHz. It has measured 19.5 dB gain at 212 GHz with a 3 dB bandwidth of 21 GHz. It draws 65 mA from a 3.3 V supply. On the other hand, a LNA was designed in a SiGe BiCMOS technology by IHP with fT/fmaxof 300/450 GHz. The LNA has measured 22.5 dB gain at 233 GHz with a 3 dB bandwidth of 10 GHz and a simulated noise figure of 12.5 dB. The LNA draws only 17 mA from a 4 V supply. The design methodology, which led to these record results, is described in detail with the LNA as an example.

Single-resonator dual-frequency AIN-on-Si MEMS oscillators.

This paper reports on the design, implementation, and phase-noise optimization of low-power interface IC for dual-frequency oscillators that utilize two high quality factor (Q) width-extensional bulk acoustic modes of the same AlN-on-silicon resonator. Two 0.5-μm CMOS transimpedance amplifiers (TIA) have been designed, characterized, and interfaced with two dual-mode resonators operating at 35.5/105.7 MHz (first/third order modes) and 35.5/174.9 MHz (first/ fifth order modes). One TIA uses open-loop regulated cascode (RGC) topology in the first stage to enable low power operation, whereas the second one uses an inverter with shunt-shunt feedback to deliver higher gain with lower phase noise. An on-chip switching network is incorporated into each TIA to change the oscillation frequency based on the different phase shift. The effect of TIA on the phase-noise performance of oscillators is studied and compared for both topologies. The measured phase noise of low- and high-frequency modes at 1 kHz offset from carrier are -114 and -108 dBc/Hz for the 35/105 MHz oscillator, and -108 and -105 dBc/Hz for the 35/175 MHz oscillator, respectively, whereas the far-from-carrier reaches below -140 dBc/Hz in all cases.

D-band Stacked Amplifiers based on SiGe BiCMOS Technology

This paper presents two 3-stage D-band stacked amplifiers developed in a 0.13-μm SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.

H-Band Power Amplifier Integrated Circuits Using 250-nm InP HBT Technology

In this paper, H-band (220-325 GHz) power amplifier (PA) integrated circuits (ICs) are presented using 250-nm InP HBT technology, where a cascode topology was adopted to achieve high gain and high output power. Three PAs were designed: PA1 was implemented with two-stage cascode HBTs, PA2 combined two PA1s, and PA3 combined four PA1s, by using Wilkinson couplers without isolation resistors. Electromagnetic simulations were carried out for the accurate design of passive circuits such as a microstrip line, a capacitor, and RF pads. The measured insertion loss of the RF pad and Wilkinson coupler was as low as 0.24 dB and 0.70 dB, respectively, at 300 GHz. The three PAs exhibited a measured gain higher than 15 dB with good return losses at 300 GHz. The output powers scaled well with total emitter area of the PAs. PA3 exhibited a maximum output power of 13.5 dBm at 301 GHz. To the best of the authors' knowledge, this corresponds to the highest output power among the previously reported solid-state PAs in this frequency range.

Design of a folded cascode opamp with increased immunity to conducted electromagnetic interference in 0.18 μm CMOS

This paper presents a folded cascode CMOS instrumentation amplifier input stage with an increased immunity to electromagnetic interference (EMI): this structure is based on a recycling folded cascode topology, and has been designed in a 0.18μm UMC CMOS process. Measurements illustrate that the modified recycling folded cascode exhibits an increased EMI immunity while preserving a satisfactory frequency response.

Design and comparison of 0.18-µm CMOS power amplifiers for ultra-wide-band applications

With the help of standard power amplifier design steps, four class AB power amplifier topologies are designed and compared using 0.18-μm CMOS process for 3-5-GHz ultra-wide-band applications. The proposed four topologies are: basic common source topology, cascode topology, cascoded current reused topology, and the two-stage power amplifier topology. Comparison of the four designs has been made to the parameters such as power gain, input and output matching, reverse isolation, power-added efficiency, stability, and linearity and noise figure. By comparison, it is found that the two-stage design with cascoded current reused topology as first stage and common source topology as second stage achieves the best performance among the four designs.

Design of RF Low Noise Amplifier at 2GHz in 0.18µm Technology

a 2Ghz Low Noise amplifier (LNa) has been implemented in Cadence spectre RF tool on UMC 0.18μm technology and is designed using a modified Cascode topology to work under reduced power supply. The input and output matching network is matched to 50Ω. after simulation it is found that at resonance frequency of 2Ghz, the forward gain is 18.22dB and reverse isolation is -40.86dB.

Fully integrated Doherty power amplifier in CMOS 65 nm with constant PAE in Backoff

Design methodology and measurements results are presented for a Doherty power amplifier (DPA) fully integrated with its input/output network matching and choke inductances in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 to 2.6 GHz show constant PAE performance starting in 20 % level up to 24 % with a maximum output power of 23.4 dBm. The circuit is fully described with all components values and layout details for further reproduction. Performance graphs showing the active load-pull effect, sub-amplifiers behavior and constant PAE prove that it is a real DPA with all effects as known by the theory. The circuit is composed by only lumped components, each sub-amplifier has cascode topology and their input/output networks are optimized to save die area and to produce a constant PAE.

An inductorless CMOS single‐to‐differential transimpedance amplifier with gain‐enhanced topology and postamplifier

ABSTRACTThis article presents an inductorless single‐to‐differential (S2D) transimpedance amplifier (TIA) with gain‐enhanced topology and postamplifier (PA) for the front‐end of an optical communication receiver. Using the regulated cascode topology with S2D converter, the proposed TIA can avoid the use of extra balance–unbalance (balun) converter. In addition, by incorporating dual active feedback in the cascaded gain stages of PA, the bandwidth of the proposed circuit can be effectively extended without using any inductor. Using a standard 90 nm CMOS process, the proposed circuit exhibits a maximum transimpedance gain of 59 dB Ω and the −3 dB bandwidth of 9.6 GHz. Operated at a supply voltage of 1.2 V, the power consumption of the fabricated circuit is only 45 mW, and maximum usable data rate is 12.5‐Gb/s. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2953–2958, 2014

An Operational Amplifier with Recycling Folded Cascode Topology and Adaptive Biasing

An Operational Amplifier with Recycling Folded Cascode Topology and Adaptive Biasing

Analysis and Optimization of Cascode Structure in Power Amplifier for X-Band Phase Array Radar Application

A 7.7---12 GHz fully monolithic transformer-coupled cascode power amplifier (PA) was designed for X-band phase array radar application. This PA was fabricated in a 0.25-$$\upmu $$μm SiGe BiCMOS technology with chip size of $$2\times 2$$2×2 mm$$^{2}$$2. The best choice of the cascode topology for PA design is discussed and the possible stability issue of this configuration is analyzed. The distributed capacitor structure which is connected to the base of cascode transistor is proposed to reduce the base series inductance and hence, improve circuit stability and boost gain. Moreover, circuit/layout co-design for above structure is completed through full 3D simulation. The PA features a three-stage cascode architecture that includes both medium-speed (medium breakdown voltage) and high breakdown voltage (low-speed) SiGe transistors, and a 1:2 input splitter and a 4:1 output combiner which are designed for a low insertion loss and compact dimensions on-chip. The proposed PA achieves a measured small signal gain of 26.6---29.6 dB from 7.7 to 12 GHz with a 5.0 V DC supply. A 28 dBm maximum output power with an 18.5 % power-added efficiency at 10 GHz have also been achieved.

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

Transparent Current Mirrors With a-GIZO TFTs: Neural Modeling, Simulation and Fabrication

This paper characterizes transparent current mirrors with n-type amorphous gallium-indium-zinc-oxide (a-GIZO) thin-film transistors (TFTs). Two-TFT current mirrors with different mirroring ratios and a cascode topology are considered. A neural model is developed based on the measured data of the TFTs and is implemented in Verilog-A; then it is used to simulate the circuits with Cadence Virtuoso Spectre simulator. The simulation outcomes are validated with the fabricated circuit response. These results show that the neural network can model TFT accurately, as well as the current mirroring ability of the TFTs.