Analysis and Optimization of Cascode Structure in Power Amplifier for X-Band Phase Array Radar Application

Abstract

A 7.7---12 GHz fully monolithic transformer-coupled cascode power amplifier (PA) was designed for X-band phase array radar application. This PA was fabricated in a 0.25-$$\upmu $$μm SiGe BiCMOS technology with chip size of $$2\times 2$$2×2 mm$$^{2}$$2. The best choice of the cascode topology for PA design is discussed and the possible stability issue of this configuration is analyzed. The distributed capacitor structure which is connected to the base of cascode transistor is proposed to reduce the base series inductance and hence, improve circuit stability and boost gain. Moreover, circuit/layout co-design for above structure is completed through full 3D simulation. The PA features a three-stage cascode architecture that includes both medium-speed (medium breakdown voltage) and high breakdown voltage (low-speed) SiGe transistors, and a 1:2 input splitter and a 4:1 output combiner which are designed for a low insertion loss and compact dimensions on-chip. The proposed PA achieves a measured small signal gain of 26.6---29.6 dB from 7.7 to 12 GHz with a 5.0 V DC supply. A 28 dBm maximum output power with an 18.5 % power-added efficiency at 10 GHz have also been achieved.