Cascaded Sigma-delta Modulator Research Articles

Design and implementation of sigma–delta digital to analog converter

This paper presents the design and implementation of a 16-bit sigma–delta digital to analog converter (DAC) for audio applications. In order to achieve high-order noise shaping without the stability problem inherent in the design of higher order loop, cascade structure may be used. One of the drawbacks in a multi-bit cascaded sigma delta modulator is the un-cancelled noise and the nonlinearity error. The idea of the proposed architecture is to present an improved version of cascaded multi-bit sigma–delta modulator to overcome these problems. Simulation results verify the superiority of the proposed modulator. Sampling rate conversion plays a predominant role in the signal processing and has a strong influence on the overall complexity and cost of efficient sigma–delta DAC. In this paper a technique to examine filter architectures that can be effectively applied in the interpolator design is also presented; the sigma–delta modulator design is implemented on a field programmable gate array (FPGA) for verification purpose and results are presented.

Design of 3rd order cascaded multi-bit sigma delta modulator for ADC using internal feedback

This paper presents a new design of third order cascaded multi-bit sigma delta modulator for analogue to digital converter. The proposed modulator is based on the conventional multibit cascaded sigma delta modulator with interstage feedback topology. Sigma delta systems favours a cascaded multi-bit architecture for higher resolution and wider bandwidth with extra effort focusing on suppressing the analogue nonlinearity. One of the major analogue non-idealities in a multi-bit cascaded sigma delta modulator is the DAC nonlinearity errors and one of the drawbacks is that performance will be limited by un-cancelled noise introducing from the nonlinear errors of multi-bit DAC. The idea of proposed architecture is to create extra feedback paths around the modulator to reduce the DAC error. In this paper, an improved version of cascaded multi-bit sigma delta modulator is proposed to overcome these problems. In addition, a third order cascaded low distortion ADC architecture is also proposed. Simulation results verify the superiority of both the proposed modulators.

Design of 3rd order cascaded multi-bit sigma delta modulator for ADC using internal feedback

This paper presents a new design of third order cascaded multi-bit sigma delta modulator for analogue to digital converter. The proposed modulator is based on the conventional multibit cascaded sigma delta modulator with interstage feedback topology. Sigma delta systems favours a cascaded multi-bit architecture for higher resolution and wider bandwidth with extra effort focusing on suppressing the analogue nonlinearity. One of the major analogue non-idealities in a multi-bit cascaded sigma delta modulator is the DAC nonlinearity errors and one of the drawbacks is that performance will be limited by un-cancelled noise introducing from the nonlinear errors of multi-bit DAC. The idea of proposed architecture is to create extra feedback paths around the modulator to reduce the DAC error. In this paper, an improved version of cascaded multi-bit sigma delta modulator is proposed to overcome these problems. In addition, a third order cascaded low distortion ADC architecture is also proposed. Simulation results verify the superiority of both the proposed modulators.

Design of Fully-Differential Switched-Capacitor Integrator for Sigma-Delta Modulator

This paper presents fully-differential switched-capacitor(SC) integrator for the third-order Sigma-Delta(SD) modulator. The proposed circuit allows rail-to-rail switching operation for the low voltage SC circuit, and it has better total harmonic distortion than the conventional circuit. This circuit provides an important block for the 2-1 cascaded SD modulator with the highresolution analog-to-digital conversion on audio codec in a communication transceiver. The switched-capacitor integrator is fabricated using 0.18μm doublepoly, triple-metal standard CMOS process with 1.8V supply voltage. The 1% settling time of the OTA consisting of SC integrator is measured to be 560ns with load capacitance of 16pF. The results showed excellent performance. The die size is 0.430×0.296㎟.

A Sigma-Delta Modulator System Design with 1-1-1 Mash Structure

This paper designs a three cascaded sigma-delta modulator with using mash structure. Analysis of gain coefficient of each module and simulate the modulator for the behavioral level. In 0.5μm CMOS process conditions, the input signal bandwidth is 20 kHz, oversampling rate is 256, SNR of the simulation model can get 100.5 dB, and accuracy is greater than 16 bit. Compared with other structures of the modulator, it has more stable and more dynamic range, so it can be applied to audio-frequency circuit.

A continuous-time cascaded delta-sigma modulator with PMW-based automatic RC time constant tuning and correlated double sampling

In continuous-time (CT) delta-sigma modulators (DSMs), cascading low-order stages provides an effective way to achieve stable high-order modulation. Compared to their single-loop counterparts, CT cascaded modulators are significantly more sensitive to variation of RC time constants and finite dc gain of the opamp as these nonidealities affect the cancellation of quantization noises between the analog and digital paths. In this paper, a pulse-width-modulation (PWM) technique is proposed for CT cascaded DSMs for on-chip automatic RC time constant tuning, which in turn enables the use of a correlated double sampling (CDS) technique to boost the effective dc gain of the opamp. A finite-opamp-bandwidth compensation technique is also proposed. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented. A prototype CT cascaded 2-2 DSM operating from a low supply voltage of 0.8V is designed and fabricated in a 0.18-μm CMOS. Measurement results show that with the proposed CDS technique the signal-to-noise-plus-distortion ratio of the modulator is 28dB higher than that of the same modulator when the CDS is turned off.

1–0–1 Cascaded Sigma–Delta Modulator with Internal Feedback

The conventional sigma---delta modulators, such as L-0 MASH and inter-stage feedback topology, have some main drawbacks, e.g. L-0 MASH can only be applied in single loop topology and dynamic range is its big problem, and inter-stage feedback topology only cancels nonlinear errors introducing by multi-bit DAC in the final stage, but the rest stages still contain DAC nonlinearity errors without any noise shaping which still degrade overall system performance. In this letter, an improved version of cascaded multi-bit sigma---delta modulator is proposed to overcome these problems mentioned above. Simulation results will verify the superiority of the proposed modulator.

Robust H-infinity filtering in finite frequency domain for polytopic systems with application to in-band quantisation noise reduction in uncertain cascaded sigma-delta modulators

This study investigates the problem of robust H∞ filtering in finite frequency domain for polytopic systems. Robust fixed-order, infinite-impulse-response (IIR) and finite-impulse-response (FIR) designs via indirect approach and direct method are presented. The aforementioned techniques refer to the conventional loop shaping method and that uses recently introduced generalised Kalman–Yakubovich–Popov (GKYP) lemma, respectively. The authors consider a frequency-domain polytopic model which includes two well-known special cases, that is, the interval plants and the set of transfer functions with affinely dependent uncertain parameters belonging to a convex-bounded polyhedral domain. They derive conditions for the existence of linear-time invariant (LTI) filters. These conditions, irrespective of the uncertain parameters, guarantee both asymptotic stability of the polytopic systems and the filters, and a guaranteed H∞ performance in finite frequency domain. Extension of the results to the multi-band case is straightforward, where the advantages of arbitrary filter order and dropping the use of weighting functions is even more obvious. As an example, the authors apply the proposed methods to in-band quantisation noise reduction for uncertain cascaded sigma-delta modulators. By comprehensive comparisons with existing methods, they show the viability and efficiency of their design.

스위치형 커패시터를 이용한 새로운 형태의 3차 직렬 접속형 시그마-델타 변조기

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is .

Mixed CT/DT Cascaded Sigma-Delta Modulator

A mixed CT/DT 2-1 cascaded ΣΔM which includes a first stage CT ΣΔM and a second stage mismatch insensitive two-channel time-interleaved DT ΣΔM is proposed. With this approach, the advantages of both CT and DT ΣΔMs including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The twochannel time-interleaved ΣΔM used in the second stage alleviates the speed constraints of the DT ΣΔM, whereas enables better matching between the analog and digital filter coefficients compared to CT ΣΔMs.

Systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators

This paper deals with a systematic approach to the synthesis of continuous-time cascaded sigma---delta modulators. Based on a system-theoretical model, a detailed derivation of the digital cancelation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal-to-noise ratio together with optimal anti-aliasing performance. By using the same model, an exact equation for the performance loss of any cascaded architecture is derived. The latter is due to the scaling for stability and given relative to an ideal high-pass filter of the overall modulator order. Finally, an analytical calculation of optimal scaling coefficients in between the stages is performed, resulting in a limited search-space for these coefficients. Theoretical results are verified by simulations.

Highly integrated front-end electronics for spaceborne fluxgate sensors

Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,…, 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability (< 5 pT °C−1 MFA temperature, < ±0.2 nT within 250 h) are very satisfying and the linear gain drift of 60 ppm °C−1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm2 mg−1.

Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time Sigma-Delta Modulators

This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigmadelta (ΣΔ) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT ΣΔ modulator in a 1.2 V 130 nm CMOS technology.

Fourth-Order Cascaded $\Sigma \Delta$ Modulator Using Tri-Level Quantization and Bandpass Noise Shaping for Broadband Telecommunication Applications

This paper presents a 14-bit cascaded sigma-delta modulator for broadband telecommunication applications. The modulator is a 2-1-1 cascaded architecture that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.5-MHz signal bandwidth, the modulator achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78.5 dB with an oversampling ratio of 16. The proposed modulator including reference voltage buffers and bandgap circuitry dissipates 62.5 mW from a 2.5-V supply. The active area is 1.2-mm2 in a 0.25-mum CMOS technology.

An $H_{\infty}$ Approach for Robust Calibration of Cascaded Sigma–Delta Modulators

In this paper, we propose a novel robust H infin optimization approach to the design of digital filters for calibrating 2-1 cascaded sigma-delta (SD) modulators. The main contribution of this paper consists of two parts. First, we develop a new filter design technique based on linear matrix inequalities applied to a model-matching problem with polytopic uncertainties in parameters. The advantage of the proposed method is that it leads to an optimal, less conservative, solution to the robust H infin filtering problem. The second contribution involves the application of the proposed robust filter design scheme to correct for inevitable and unwelcome analog imperfections typically associated with cascaded SD modulators. For numerical illustration we concentrate on the 2-1 architecture. Simulation results for a range of parameter excursions suggest that our robust H infin filter guarantees an improved signal-to-noise ratio performance over the nominal filter.

Robust Calibration of an Improved Delta-Sigma Data Converter Using Convex Optimization

In this paper, we analyze that analog circuit imperfections in the cascaded delta-sigma modulators may lead to the incomplete noise cancellation from the earlier stages, as well as non-unit transfer function from the input signal to the output, resulting in the degradation of signal-to-noise ratio (SNR) performance. It is difficult to design one digital filter to compensate the effects from both the incomplete noise cancellation and non-unit transfer function. We therefore proposed a novel architecture of cascaded delta-sigma modulators which consist of feedforward and feedback loops. Under this structure, the transfer function from the input signal to the output is always unit even though there exist analog circuit imperfections. The rest of the design therefore, is only to consider to reduce the effect of the incomplete noise cancellation as small as possible, which is formed as a robust H2 optimization problem. This problem can be recast as a convex optimization problem by the change of variables, congruence transformations and Schur complement, which is easily solved by reliable and efficient numerical algorithms. To prove the advantages of the architecture and the design method, we conduct numerical simulations on 2-2 cascaded delta-sigma modulators. Simulation results for a range of parameter excursions show that our proposed filter improves SNR performance over the nominal filter greatly.

On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma–Delta Modulators

This paper deals with one of the most outstanding advantages of continuous-time (CT) sigma-delta modulators compared to their discrete-time counterparts: the implicit anti-aliasing feature (AAF). Although inherent in any CT architecture, analysis of anti-aliasing properties has mostly been restricted to single-stage modulators in the past. In this contribution, extensions on analysis methods for the study of the AAF of CT multistage noise-shaping architectures are covered. A theoretical model is introduced and confirmed through simulation results. Contrary to previous belief, the results indicate that usually all stages of a cascaded architecture are involved in the anti-aliasing behaviour and hence that it is not solely determined by the first stage.

Robust H2 Approach for Digital Correction of Cascaded Sigma Delta Modulators

In this paper, we present a robust H2 approach to digitally correct for analog circuit imperfections in a 2-1 cascaded sigma delta modulator. A low-order filter with the same order of the nominal filter is designed, which can efficiently handle a more substantive deviation of the coefficients of the analog filter away from the design values without any extra implementation burden. Simulation results show that the proposed filter provides a strong robustness to circuit imperfections and guarantees an improved signal-to-noise ratio performance over the nominal filter.

Reconfigurable ADCs enable smart radios for 4G wireless connectivity

A reconfigurable ADC based on a 2-2 modified cascaded SigmaDelta modulator designed for a GSM/WCDMA/WLAN/WiMAX zero-IF receiver has been presented. Employing the second-order feedforward SigmaDelta modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth is achieved. The P-DWA technique is applied in the first feedback 4-b DAC to eliminate the spurious tones associated with the multibit DAC nonlinearity in the WLAN/WiMAX modes

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs

This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ modulators.