Carry Skip Adder Research Articles

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

Implementation of Carry Skip Adder using Carry Select Adder with Improved Area, Delay, and Power Efficiency

This paper presented a Carry Skip Adder (CSKA) structure with less area, less delay, and lower power consumption. This can be achieved with Carry Select Adder's (CSLA) help. The proposed structure uses AND-OR-INVERT (AOI) and OR-AND- INVERT (OAI) compound gates for the skip logic. The use of Carry Select Adder will reduce the number of LUTs used (i.e.) the area of the proposed structure, reduce delay in performing processes, and also reduce power consumption. Simulation of the proposed hybrid CSKA-CSLA structure reveals a reduction in area, delay, and power consumption compared with the CSKA-RCA structure and with the latest works in the field. The simulation results reveal the improvementinareabyreducingthenumberofLUTsfrom91to79 and in delay by reducing the time required to process from 39.969ns to 35. 258ns and power consumption by reducing the power required to process from 64.44 mW to 64.41 mW when compared with the CSKA-RCA structure. This project used the Xilinx ISE tool to simulate the Area and Delay Analysis and the AlteraQuartusI Itool to simulate the Power Analysis.

Distributed arithmetic-FIR filter design using Approximate Karatsuba Multiplier and VLCSA

In this manuscript, a High Throughput and Low Latency DA-FIR filter design is integrated with Approximate Karatsuba Multiplier (AKM) and Variable Latency Carry Skip Adder (VLCSA) is proposed for the noise removal application in SDR. In this design, an AKM and VLCSA are considered to decrease the count of partial products on DA framework, although no multiplication is clearly performed. Thus, an important reduction is accomplished under accumulation circuits. The main execution problem of the DA system is the size of lookup table (LUT) increases exponentially through the length of inner product. To further diminish the memory complexity, approximate DA architectures depending truncation approach are needed. Partial products on DA are created through truncating least significant bits (LSBs) of inputs. The proposed hybrid technique lessens a count of LUTs by truncating the least significant bits of input operands. To further reduce the latency, this manuscript deals with one of the fastest multipliers, namely Approximate Karatsuba Multiplier employed for accumulation of partial products. The proposed design is performed in Verilog using Xilinx 14.5 ISE simulation. The experimental performances of the proposed DA-FIR-Hyb AKE-VLCSA filter is evaluated under lower delay, lower static power and compared with the existing filters.

Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration

Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this balance, significantly improving the performance of digital systems. Here, a 5-bit adder with a unique configuration is used in place of a Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA). Using CMOS & TG Configuration, all other internal structures have been created. Performance comparisons of the CMOS and TG 5-bit Adders with the adders above are shown in terms of power, latency, and area. Various adders: 5-bit Adder with CMOS & TG design, the CMOS & TG based CLA, the CSA, and the RCA, are also involved in the multiplier's adder unit selection process. The new multiplier provides the perfect answer for energy-efficient designs by combining low power consumption with small size.

A Way to Optimize Delay of Carry-Skip Adders by Using Blocks of Variable Sizes

As one of the most common operational modules in computer processors, the optimization of the propagation delay of adders has attracted extensive attention of researchers. This article proposes a method of optimizing the delay of carry-skip adders by using blocks of variable sizes. By increasing the sizes of the bypass stages gradually and then decreasing it stage by stage, keeping the delay of the first and last stage short, the total propagation delay is optimized. Compared with fixed size carry-skip adders, the delay of variable sizes carry-skip adders has a square root relationship with the number of bits. Thus, when the number of bits is large, the propagation delay is significantly reduced. After calculation, when the number of bits is 16, the propagation delay decreases by 16.67%, and when the number of bits is 256, it decreases by 52.78%. Due to the shorter propagation delay, variable sizes carry-skip adders have faster operation speed and can be applied to improve the performance of computer processors.

Design and analysis of a novel fast adder using logical effort method

AbstractAddition, as one of the fundamental math operations, is applied widely in Very‐large‐scale integration systems and digital signal processing, such that the computational speed of a system depends mainly on the computational speed of its adders. There are various types of digital adders based on different methods. A novel adder is proposed which performs addition based on a path with a fewer number of levels, and, hence, with higher computational speed and lower power consumption. The goal and innovation is to design a structured fast adder that has a block that can be expanded to higher bits, and in this design, the calculation speed and power consumption of the proposed circuit are optimal. Each proposed adder circuit has several levels, and the formulae of each level are stated. Each level of the circuit is designed with a number of multiplexers and OR gates. The performance of the proposed adder has been investigated and evaluated in two parts of mathematical calculations and simulation, and it has also been compared with other existing fast adders, such as ripple carry adder, carry skip adder, carry select adder, carry look ahead adder and prefix kogge‐stone in cases of 8, 16, 32 and 64 bits. The results show that the proposed collector has a good performance compared to other adders‐based power consumption, power delay product and delay area product metrics.

ALL-OPTICAL CARRY SKIP ADDER WITH THE HELP OF TERAHERTZ OPTICAL ASYMMETRIC DEMULTIPLEXER-BASED SWITCH

The terahertz optical asymmetric demultiplexer (TOAD) or semiconductor optical amplifier (SOA)-assisted Sagnac switches have been used to construct an all-optical 4-bit carry skip adder. This design aims to satisfy the high speed and accuracy requirements of modern ultrafast digital transmission. Using a combination of an all-optical multiplexer and an all-optical full adder, we describe an all-optical carry skip adder. When compared to ripple carry adder and carry look-ahead adder, carry skip adder may be employed to create a fast arithmetical processing unit. Numerical simulation is used to develop and validate this theoretical model.

An Accelerated Variable Stage Size Carry Skip Adder Realization Using 1S1R Resistive Memory

In-memory computing is the method of running computer computations completely in memory. Memristive device (e.g., 1 selector-1 resistor (1S1R)) is preferably utilized for in-memory computing with the appearance of hybrid CMOS nano-crossbar arrays. The parallelism of resistive arrays is considered in parallel adder designs to reduce the critical path delay. However, they minimize latency at the cost of hardware resources. In addition, the resistive random-access memory (ReRAM) is suffered by sneak–path problem because of the incapability for accessing a specific cell without impeding its neighbors. To tackle this issue, an analytical model of Pt/TaO[Formula: see text]/TiO2/TaO[Formula: see text]/Pt selector device is developed and it is integrated with ReRAM model for reducing the sneak path current. In this paper, a novel mapping scheme is proposed for in-memory variable stage size carry skip adder (VSS-CSKA) to harness the parallelism of 1S1R resistive memory. The VSS-CSKA considers variable block lengths and uses basic Boolean functions as skip logic to improve the speed without requiring huge area. Also, the selector device is modeled by considering the Pt/TaO[Formula: see text]/TiO2/TaO[Formula: see text]/Pt crested barrier for suppressing the sneak current in the resistive memory. The macro-model of the 1S1R resistive memory model is modeled in Verilog-A netlist and the simulations are executed on Spectre circuit simulator from Cadence Virtuoso. The proposed in-memory adder reduced the latency to [Formula: see text] for [Formula: see text]-bit addition and it consumes less energy because of the minimization of sneak currents in 1S1R.

Performance optimization of the nano-scale carry-skip adder based on quantum dots and its application in the upcoming Internet of Things

Internet of Things (IoT) is a network of linked computers, electronic and mechanical equipment, objects, living things, and people that can exchange data without human-to-human or human-to-computer interaction. Real objects with sensors, computing power, software, and other technologies are called IoT when they connect to and exchange data with other systems and devices over the Internet or other communication networks. On the other hand, Quantum-dot Cellular Automata (QCA) is a highly appealing alternative to transistor-based technologies for future circuit design, thanks to its excellent performance and low power consumption characteristics. Therefore, researchers are trying to implement IoT-related circuits in this technology and take advantage of it. In IoT nodes, the circuits were previously designed based on transistors and used extensively are adder circuits and their various forms, such as carry-look-ahead adder, ripple carry adder, and Carry-Skip Adder (CSA). The proposed CSA is part of the bypass adder family, and its major goal in IoT devices is to reduce latency and power consumption. Designing CSA is a fascinating area of research in the QCA and IoT domains. In this research, we will offer nano-scale CSA designs based on logic gate structures. This CSA aids in improving system performance in terms of average power dissipation, area, and delay. This design has performed admirably in terms of physical qualities, particularly power usage. As a result, an ultra-low-power CSA is proposed, which employs a reduced number of cells and a smaller area while achieving the desired highly polarized output. All the circuits provided in the simulator software have been tested, and their correctness has been confirmed. 36 quantum cells were employed, and the adder's area with propagating signal is around 0.04 µm2. The latency is about 2 clock phases. Additionally, the CSA for IoT devices is roughly 0.4 µm2, which results in a delay of 17 clock phases and the need for 374 quantum cells. The suggested CSA reduces cell consumption by 64 %, improves latency by 15 %, and increases area by 85 %. Compared to a carry-look-ahead adder, the CSA is the only way to reduce the latency of a ripple carry adder with low effort.

Design and Implementation of Area Efficient 16-bit Carry Skip Adder

Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area and delay are analyzed using Xilinx ISE 14.7. The hardware simulation is done in Xilinx Spartan 3E FPGA.

Mitigation of Critical Delay in the Carry Skip Adders Using FinFET 18nm Technology

In this paper optimization of full adder in 3-dimensional (3-D) using Fin Field Effect Transistor (FinFET) with Gate Diffusion Input (GDI) is proposed to optimize critical delay, power. FinFET technology is more suitable for below 10nm technology process. The major aim of this work is to indemnify significant factor in adder structure i.e. critical delay. Pipelining architecture is enforced to accomplish the objective with the aid of FinFET 18nm technology. The structure is optimized to get the minimum delay confinement. Suggested design needs less logic resources. The outcomes are validated using FPGA synthesis methods. By applying the FinFET technique, we developed adder topology yielding up to 90% performance improvement with respect to delay, power and area compared to the conventional adders. The simulation was carried out with low power cds ff mpt PDK. The study also includes a carry skip adder design for FPGA implementation.

The Design of Digital System with CSA

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and ORAND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

Power Minimization by Designing Novel Architecture for Multimodal Biometric System

Abstract: The reduction of power, area, and delay parameters are increasing as the range of sophistication of applications in VLSI circuit designs. Adders and multipliers play a vital role in VLSI circuit designs to minimize the power consumed by the circuit. The Finite Impulse Response Filter is widely used in Digital Signal Processing Applications, such as speech processing, loudspeaker equalization, echo cancellation, noise cancellation, arithmetic computations and, image-processing applications. In FIR filter, the adders and multipliers are the important components to reduce the power, delay and area. Therefore, this proposed method faced with more constraints: as minimal power as possible. This work proposes a design of low power Finite Impulse Response Filter using Carry Skip Adder.The recent electronics industry uses digital filters for various real time applications. A novel VLSI architecture is designed by using ALU based FIR filters for biometric system. Where in ALU includes adders and multipliers, comparing different adders for there better performance with respect to power and identifying carry skip adder will consume less power compared to other adders. power consumption of overall architecture by including carry skip adder is very less and we can use this same adder for multimodal architecture also.

High-Speed 16-bit Carry Bypass Adder Design

Adders are one of the most significant blocks in a logical arithmetic unit. These are employed in a wide range of applications, from incrementing the value of a program variable to high-speed applications such as video-encoding, digital-signal. There are various adders with varying propagation delays. As a result, selecting an efficient adder is critical for system performance. This research compares the latency of several 16 bit adders that are available. The delay of logic gates in 180nm technology has been quantitatively modelled utilizing logical effort. The delay is then utilized to calculate the delay of various adders in Virtuoso Cadence while simulating. Virtuoso Cadence was used to perform functional verification on adders. Each adder's route delay has also been determined. Based on this research, a new carry bypass adder has been developed to reduce propagation delay. The suggested carry bypass adder reduces combinational path latency by 7.2 percent and logical effort delay by 29.5 percent, respectively. Keywords: Algorithms for 16-bit adders, logical effort, propagation delay, carry skip adder

Comparative Analysis of Vedic Multiplier using Various Adder Architectures

The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.

A Delay Efficient Hybrid Parallel Prefix Variable Latency CSKA Based Multi-Operand Adder with Optimized 5:2 Compressor and Skip Logic

In this paper, a delay efficient multi-operand adder (MOA) is introduced by considering the compression logic and variable latency carry skip adder (VL-CSKA). Here, an optimized 5:2 compressor is initially used to increase the speed of MOA by reducing the number of operands before giving as input to VL-CSKA. Also, the VL-CSKA is modified by replacing the carry propagation with complementary complex gates (CCG) and nucleus stage with improved parallel prefix structure for increasing the speed with fewer components. The delay, area, power, and logic depth of the proposed hybrid parallel prefix VL-CSKA (HPP-VL-CSKA) is also reduced by modifying the group Propagate-Generate (PG) logic in the parallel prefix structure. Also, a new circuit for XOR/XNOR gate is used for the reduction of the delay and power consumption significantly. The synthesis result shows that the suggested adder design overtakes the existing adders by consuming only 5953 area, 1.763power, 1.251fJ and 3516.63 ADP for 20 number of operands, each with 32 bit inputs.

Low Area and Power-Efficient FPGA Implementation of Improved AM-CSA-IIR Filter Design for the DSP Application

Digital Signal Processing (DSP) grew enormously in the past few decades and it was extensively practiced for numerous engineering applications like biomedical signal processing, radar signal processing, adaptive antenna design, intelligent control, etc. In DSP, the Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter plays a vital role in the design of a complex signal processing system. Generally, The FIR filters are stable, linear in phase, with fewer finite-precision errors and easy to implement. However, most of the IIR filters are used in signal processing applications due to the less computational complexity which is compared to the FIR filters. Moreover, the IIR filter requires only fewer filter coefficients and requires only less amount storage registers. In this research, an IIR filter is implemented with Array multiplier and Carry Skip Adder (CSA) to improve hardware utilization. The IIR filter input is generated randomly which is stored in Random Access Memory (RAM). Similarly, the coefficient is generated by utilizing the Parks-McClellan algorithm where the generated value is stored in Read Only Memory (ROM). The proposed AM-CSA IIR (Array Multiplier-Carry Skip Adder Infinite Impulse Response) filter performances are evaluated in terms of filter output, Input Output Block (IOB), Look Up Table (LUT), Flip Flops (FF), slices, delay, and fractional delay. Overall the proposed design attained LUT= 115 (0.0564%), FF=40 (0.01%) and IOB= 22 (3.77%) and reduced fractional delay of about 0.0057ns.

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.

A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine the system overall speed. To improve noise margins, the threshold voltages must also be made smaller. However subthreshold leakage current increases exponentially when threshold voltage is reduced. The higher static dissipation may then offset the reduction in transitions portion of the dissipation. Hence the devices needed to have threshold voltages that maximizes the net reduction in the dissipation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Due to the potential versatility of adders in this contemporary research field, the existing adders and adder designs currently intended for future low voltage and low power environments. This can be achieved by the CMOS adders namely Parallel Adder, Ripple Carry Adder(RCA), Carry Look Ahead Adder(CLA), Carry Select Adder(CSL), Carry Save Adder(CSA), Carry Skip Adder(CSK), Conditional Sum Adder(COS).