Carry Save Adder Research Articles

High – Speed and Low Area-Efficient VLSI Architecture of Three-Operand Binary Adder

Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three- operand addition. In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three-operand addition that significantly reduces the critical path delay with more area complexity. Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed method is designed using Xilinx ISE 14.7

High Efficiency Carry Save Adder using Modified–gate Diffusion Input Technique

Addition is a fundamental function in the design of a digital system, necessary for applications such as signal processing, arithmetic operations, multiplexers, and control systems. Hence, the digital system’s performance is considerably reliant on the efficiency of the adders. Therefore, designing a 4-bit carry save adder (CSA) that consumes less power, occupies a smaller area, and operates at a higher speed is proposed using the modified–gate diffusion input (MOD–GDI) technique. The primary focus is to reduce the area occupied by decreasing the transistor count as compared with other logic styles (i.e., conventional, and Boolean simplification) for CSA through Cadence Virtuoso simulation based on SilTerra 180 nm technology. Notably, the number of transistors is reduced from 42 in the conventional full adder to 11 in the proposed MOD–GDI design. As a result, the proposed 4-bit CSA with MOD–GDI technique is efficient in improving the speed of addition by reducing the area and power consumption.

Design and Implementation of Braun Multiplier using Verilog: Research

Abstract: Multiplication is widely used in places like digital signal processing, image processing, instrumentation that require multilayer components. Carry Save Adder and ripple carry adder both are used in parallel processing architecture. They are widely used for signed multiplication i.e. for both negative and positive numbers. We have now designed a Braun multiplier (BM) to improve the speed, power and area capability. We are using the Xilinx tool to verify Braun multipliers using Verilog. We are taking the following considerations: checking using FPGA based instruments and implementing code using Verilog-VHDL. The adders are integrated into multipliers. The result of this research is to modify BM to improve the performance along with reduction in power consumed and also using less area.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations

Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay. Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operation. The canonical types of PPA result in a lesser path delay of approximately O (log2 n). These adders can be designed for 8, 16, 24 or n bits. But this work is focused on developing a 24-bit three-operand adder that takes three 24-bit binary numbers as input and generates a 24-bit sum output and a carry using five different PPA methods The proposed summing circuits are operationalized with Hardware-Description-Language (HDL) using Verilog, and then subjected to synthesis using Field -Programmable Gate- Array (FPGA) Vertex 5. On comparing the proposed adders, it shows that the delay and the size occupied are significantly less in the Sklansky PPA. These faster three-operand adders can be utilized for three-operand multiplication in image processing applications and Internet of Things (IoT) security systems.

Finding the longest delay paths for the array-form multipliers using a genetic algorithm

Traditional digital multipliers are often designed in array forms or other variants. Timing of array-form multipliers can be analyzed by static timing analysis (STA), but the obtained timing result is conservative and pessimistic. Although statistical static timing analysis (SSTA) can partly solve the pessimism, it still does not generate test patterns for those near-to-longest delay paths. Finding near-to-longest delay paths can be helpful to designing error tolerant circuits, with which aggressive timing (with timing violation) can be exploited. In such design scenarios one should find test vectors to activate those near-to-longest delay paths in order to further run SPICE-precision diagnose on those potential timing violating critical paths. Test vector generation for such a testing problem is essentially an exhaustive enumeration problem when dealing with different forms of array multipliers. However, large size multipliers would result in an extremely large enumeration space for finding the longest delay path (LDP) test vectors. Currently there is no deterministic method that can guarantee to find test vectors for exact LDPs of a large size multiplier. Only very few research papers have addressed this problem, proposals are limited to heuristic methods without guarantee of finding the LDPs with the testing vectors. This paper investigates the potential of a genetic algorithm (GA) for searching the extensive test pattern space. By a fine design of GA, experimental running shows that a combination of well tuned evolutionary operators does empower the possibility of finding the LDPs for a set of moderate size carry-save adders (CSA) multipliers with the wordlength (WL) up to 25 bits on a plain laptop computer. Statistical properties of the proposed GA are examined.

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration

Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this balance, significantly improving the performance of digital systems. Here, a 5-bit adder with a unique configuration is used in place of a Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA). Using CMOS & TG Configuration, all other internal structures have been created. Performance comparisons of the CMOS and TG 5-bit Adders with the adders above are shown in terms of power, latency, and area. Various adders: 5-bit Adder with CMOS & TG design, the CMOS & TG based CLA, the CSA, and the RCA, are also involved in the multiplier's adder unit selection process. The new multiplier provides the perfect answer for energy-efficient designs by combining low power consumption with small size.

On the Commutative Operation of Approximate CMOS Ripple Carry Adders (RCAs)

On the Commutative Operation of Approximate CMOS Ripple Carry Adders (RCAs)

Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology

The semiconductor industry’s continuous effort to miniaturize and be more powerful to increase the overall performance. This has led to the use of FinFET technology for packing more transistors into a smaller space and using power more efficiently compared to planner MOS technologies. Compared to the MOS technology, FinFET technology provides better advantages such as improved transistor performance, lower leakage currents, and enhanced power efficiency. The proposed work includes integrating fundamental components like the NAND gate, 2:1 MUX, and full adder (FA). These components are combined to build both Ripple Carry Adder (RCA) and Carry Save Adder (CSA). The work is carried out using 7nm FinFET technology and this research involves a thorough analysis of power consumption and propagation delay, with the implementation carried out using the Cadence Virtuoso tool. The study highlights the improved performance of 7nm FinFET technology compared to MOSFETs.

Implementation of Ripple Carry Adder Design for Optimal VLSI Performance

In the province of wireless receivers, biomedical equipment, and portable/mobile devices, the demand for Very Large Scale Integration (VLSI) systems that optimize space, minimize power consumption, and deliver high performance is dominant. At the core of these systems, adders play a pivotal role as the primary component of arithmetic units. This paper proposes a ripple carry propagate adder with a high-speed area-efficient. The two’s complement representation is employed for adding two numbers, a common practice in various systems dealing with n-bit input sequences. Microprocessors and digital signal processing use these carry adders. The carry output of every finished adder stage is useful as a carry input to the one behind it. This procedure is continued until the last complete adder stage is reached. Each carry output bit in an entire adder is therefore rippled to the next stage. An exact (forward) carry adder be linked with the proposed structure to generate hybrid adders with tunable accuracy levels. The practical implementation of proposed model is carried out using Xilinx ISE Design Suite 13.4, showcasing its feasibility for real-world applications.

Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination

Quantum dot cellular automata (QCA) stands as a highly promising nanotechnology, capable of outperforming conventional CMOS technology. Leveraging its advantages, this paper addresses the challenges in adder circuits related to size, delay, and cost by integrating QCA technology. A novel layout for a co-planar full adder in QCA is introduced, featuring a half-adder design with 23 cells in a single layer without any crossover, achieving a delay of 0.25 clock cycles. By utilizing inter-cellular effects inherent in QCA technology, the presented designs offer significant improvements in a variety of design metrics, and a cost efficiency of 64.3%, distinguishing them from traditional logic design approaches. Additionally, in order to ensure an efficient routing channel and a consistent structure of the adder design, a Universal, Scalable, and Efficient (USE) clocking scheme has also been employed. The adder design is further used to build 4-bit and 8-bit Ripple Carry Adders. An extensive study on energy dissipation using QCADesigner-E and QCAPro tools is conducted for three tunneling energies (0.5 Ek, 1 Ek, and 1.5 Ek). The full adder design showcases substantial improvement in energy to delay cost when compared to the closest reported design, achieving improvements of 91.66%, 89.03%, and 88% at 0.5 Ek, 1 Ek, and 1.5 Ek, respectively. The results highlight enhanced circuit efficiency and streamlined layouts, outperforming existing models and offering substantial benefits to high-performance and energy-efficient computing systems.

Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors

This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a power of 572.063uw, delay 0.32ns and PDP 183.06 fj. The outcomes obtained are compared with existing models. For characterstics of speed and PDP, the proposed model outperforms existing models significantly. The circuit was designed in 90nm GPDK technology by using the CADENCE VIRTUOSO TOOL.

High Performance, Low Power Wallace Tree Multiplier

An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multipliers. To enhance the performance of circuits and systems, the design of multipliers is very important. The key feature of a high-performance Wallace tree multiplier lies in its efficient reduction of partial product additions. By utilising a combination of carry-save and carry-propagate adders, it minimises the critical path delay and maximises the speed of multiplication. Additionally, advanced optimisation techniques such as parallel prefix adders and parallel carry-save adders can be employed to further improve performance.

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Numerical Model for 32-Bit Magnonic Ripple Carry Adder

In CMOS-based electronics, the most straightforward way to implement a summation operation is to use the ripple carry adder (RCA). Magnonics, the field of science concerned with data processing by spin-waves and their quanta magnons, recently proposed a magnonic half-adder that can be considered as the simplest magnonic integrated circuit. Here, we develop a computation model for the magnonic basic blocks to enable the design and simulation of magnonic gates and magnonic circuits of arbitrary complexity and demonstrate its functionality on the example of a 32-bit integrated RCA. It is shown that the RCA requires the utilization of additional regenerators based on magnonic directional couplers with embedded amplifiers to normalize the magnon signals in-between the half-adders. The benchmarking of large-scale magnonic integrated circuits is performed. The energy consumption of 30 nm-based magnonic 32-bit adder can be as low as 961aJ per operation with taking into account all required amplifiers.

Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers.

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.

Design of Multiplier Circuit Using Carry Save Adder Based on Quantum-Dot Cell Automata

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.

DESIGN OF AN FIR FILTER USING RIPPLE CARRY ADDERS AND VEDIC MULTIPLIERS

We would like to congratulate you on the successful publication of your research paper in our journal! International Journal of Scientific Research in Engineering and Management (IJSREM) on Volume 07, Issue 03 March 2023. Paper Title: DESIGN OF AN FIR FILTER USING RIPPLE CARRY ADDERS AND VEDIC MULTIPLIERS Your hard work has been noted and appreciated by us, and we thank you for showing interest in our journal. Your work is now visible to the world, and as an appreciation of your contribution we enclose with this email e-certificate of all the author(s) as a token from us.