Carry Propagation Delay Research Articles

Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling

The new generation of electronic circuits based on spintronic technology have drawn the attention of researchers in recent years due to their remarkable features, including low-power consumption, non-volatility, and compatibility with the CMOS technology. However, these circuits usually rely on the pre-charge sense amplifier (PCSA), to read the state of the magnetic tunnel junctions (MTJ). The major disadvantage of the PCSAs is the high sensitivity of these circuits to inputs scheduling. It means that if the inputs are not applied to the circuit exactly in the specified time, the generated output will not be valid. This issue causes a serious problem in the ripple carry adders due to their carry propagation. In this paper, a novel structure is proposed which is based on removing MTJ from carry propagation path by adding a post-processing unit. The proposed post-processing unit makes the spintronic adders invulnerable to inputs scheduling. The proposed adder in this paper occupies at least 29% less area. It also offers 40% lower carry propagation delay, and 37% lower power-delay product compared to the efficient state of the art counterpart.

Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.

A Novel Design of High-Performance Hybrid Multiplier

In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.

Area-Power Analysis of Carry Select Adder using Transmission gates

The main building block of microprocessors, microcontrollers, and digital signal processors is an arithmetic logic unit (ALU). The performance of ALU depends on its adder design. The Carry Propagation Delay (CPD), area and power are the important metrics in the structure of the adder. In this work, area and power analysis of carry select adder are presented. In this adder, the CPD is minimized with the common Boolean logic. The power and area of the adder are optimized by replacing CMOS gates with transmission gates. In this technique, the transistor count is greatly reduced from 987 to 512 for a 16-bit carry select adder. In addition, the power consumption is minimized from 0.63mW to 0.018mW and the power delay product is minimized from 0.53mW-ns to 0.021mW-ns.

Area-Delay-Power analysis of Carry Look-AheadAdder Architecture

The addition is common in hardware for the microprocessor and digital signal processor (DSP), and an adder is used to execute the addition. The Adder should feature high speed and low power for real-time applications. An effective adder architecture principally advances the performance of microprocessors and DSP systems. The carry propagation delay (CPD) is the main apprehension in the design of adder architecture. To address CPD, a new Carry Look-Ahead architecture is proposed, in which the carry propagation is scheduled before the calculation of the final sum using carry look–ahead (CLA) method. A quantitative estimate shows that the Area Delay Product (ADP) of proposed adder architecture is minimized by 10% as compared with the existing adders’ architectures.

Parallel Self-Timed Adder with Lookahead-Carry Generator

Parallel self-timed adder (PASTA) is a newly introduced asynchronous adder. It shows appreciable average-case performance without any special speedup circuitry or look-ahead schema, but its worst-case performance is almost similar to that of ripple carry adder. It is therefore an important research issue to find a technique to improve its worst-case performance without any significant compromise in its other performances. This paper investigates the possibility of such performance improvement of the basic architecture of PASTA by changing its carry propagation schema. The existing ripple fashioned carry propagation schema is replaced by four different lookahead-carry generators. Four different implementations of PASTA with four different types of lookahead-carry generators are presented. The carry propagation delays of the proposed implementations are compared with that of the basic implementation of PASTA. More impressive worst case performances are found for the proposed implementations. The amount of improvement is minimum 45.25% and maximum 61.09%. The proposed designs are regular and do not have any practical limitations of fan-ins or fan-outs. Simulation-based results validate the practicality as well as the superiority of the proposed architecture over the existing architecture of PASTA.

Updated Efficient Area -Carry Select Adder for Low Complexity D LATCH Configuration by disease identification in brain tumor hyper spectral image

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime [Formula: see text] is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye’s double and add (DAA) algorithm based on [Formula: see text]-only common [Formula: see text] (co-[Formula: see text]) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47[Formula: see text]ms at a maximum frequency of 327[Formula: see text]MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and [Formula: see text] metrics.

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

In this paper, a novel 8-bit approximate multiplier is proposed based on three novel 4:2 approximate compressors which its delay and error is less than those of the multipliers constructed by traditional 4:2 approximate compressors, and its delay is also less than that of an 8-bit multiplier constructed by using 3:2 precise compressors. To do so, each novel compressor is designed such that its output carry is independent of the output carry of its previous compressor in the multiplier. Therefore, the problem of carry propagation delay is eliminated and a fast multiplier is constructed. To obtain the most accurate multiplier, the best compressor of the three proposed compressors for each multiplier’s column is determined using the genetic algorithm. Moreover, one can use the approximate compressors only at the k least significant multiplier’s columns for more error reduction. The proposed multiplier is used for image blending and image compression. Our simulations show that for example the error and the delay of the proposed method for k =9 is at-least 32.52% and 33.10% less than those of traditional 4:2 approximate compressor based multipliers, respectively. Normal 0 false false false EN-US X-NONE AR-SA /* Style Definitions */ table.MsoNormalTable {mso-style-name:Table Normal; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:Calibri,sans-serif; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Times New Roman; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:Arial; mso-bidi-theme-font:minor-bidi;} Abstract : In this paper, a novel 8-bit approximate multiplier is proposed based on three novel 4:2 approximate compressors which its delay and error is less than those of the multipliers constructed by traditional 4:2 approximate compressors, and its delay is also less than that of an 8-bit multiplier constructed by using 3:2 precise compressors. To do so, each novel compressor is designed such that its output carry is independent of the output carry of its previous compressor in the multiplier. Therefore, the problem of carry propagation delay is eliminated and a fast multiplier is constructed. To obtain the most accurate multiplier, the best compressor of the three proposed compressors for each multiplier’s column is determined using the genetic algorithm. Moreover, one can use the approximate compressors only at the k least significant multiplier’s columns for more error reduction. The proposed multiplier is used for image blending and image compression. Our simulations show that for example the error and the delay of the proposed method for k =9 is at-least 32.52% and 33.10% less than those of traditional 4:2 approximate compressor based multipliers, respectively. Normal 0 false false false EN-US X-NONE AR-SA /* Style Definitions */ table.MsoNormalTable {mso-style-name:Table Normal; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:Calibri,sans-serif; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Times New Roman; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:Arial; mso-bidi-theme-font:minor-bidi;}

Radix-8 full adder in QCA with single clock-zone carry propagation delay

We design a 3-bit adder or a radix-8 full adder (FA) in quantum-dot cellular automata (QCA), where the 3-bit carry propagation path can be accommodated in one clock-zone. To achieve this, we introduce group majority signals similar to group propagate and generate signals in parallel prefix computations, use them to reformulate the carry expressions of a previous radix-4 FA, and as such we could extend it to higher radix FAs. Applying the aforementioned new interpretation of carry expressions (via group majority signals) on 3-bit adders, results in that only a single clock cycle is required for 12-bit (vs. the previous 8-bit) carry propagation, across four radix-8 FAs. Based on the proposed radix-8 QCA-FA, we realized 8-, 16-, 32-, 64, and 128-bit QCA adders via QCADesigner. Comparison of these adders with the previous radix-4 experiment, showed 9–41% speed up, and 57–76% area saving, for 16–128-bit adders, respectively. On the other hand, compared to the best previous radix-2 design, for the same bit widths, we experienced 57–172% speed up, but at the cost of 138–4% area increase, except for the 64 and 128-bit cases, where we also experienced 19% and 41% area saving, respectively.

CNTFET-based design of multi-bit adder circuits

ABSTRACTThis paper presents a novel design of a high performance full adder cell based on carbon nanotube field-effect transistors (CNTFET). This full adder cell has been designed to be used in ripple carry adder (RCA) optimally so that carry-propagation delay decreases without increase in hardware costs. High speed in RCA structure, the low number of transistors and simplicity in design are the main advantages of the proposed design in comparison with the previous works. Moreover, to increase the proposed RCA speed, carry-propagation chain has been reduced to six cells using only 14 transistors per 4 bits in the worst case, regardless of the adder width. The simulation results using HSPICE demonstrate that a significant improvement in delay, power and power-delay product compared with the state-of-the-art works can be achieved. The results in different temperatures, supply voltages, frequencies and load capacitors have also been obtained.

An Area Efficient 32-bit Carry-select Adder for Low Power Applications

CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [1]. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input Cin=0 and cin=1, then the final sum and carry are selected by the multiplexers (mux). The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position.

A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.

Design of a high-efficient MSD adder

Carry propagation delay is a big obstacle to improve the addition efficiency in computer system. And the more data bits the operands have, the delay is more serious. As data bits of operand in optical computer can be huge this makes carry delay be very serious. How to decrease or even mitigate carry delay in addition is very important to promote optical computer in numerical computing applications. To improve the addition efficiency, a new method to design and implement optical adder is put forward. Fully considering the relations between the addend and augend based on modified signed-digit (MSD) number system operands, division algorithm is presented. It makes the design and implementation of the adder much easy and feasible. Besides, it also guarantees that no carry delay is introduced in the process of addition. Meanwhile, the architecture of the adder, its implementation as well as the auxiliary electronic circuit are also presented. Experimental results show that the architecture and design of the new MSD adder are correct. It can avoid carry propagation and is much efficient for optical addition operation.

Low Power, Area Efficient & HighPerformance Carry Select Adder on FPGA

LOW-POWER, area-efficient, and high-performance VLSI systems are increasingly used in portable and mobile devices, multi standard wireless receivers, and biomedical instrumentation. An adder is the main component of an arithmetic unit. A complex digital signal processing (DSP) system involves several adders. An efficient adder design essentially improves the performance of a complex DSP system. A ripple carry adder (RCA) uses a simple design, but carry propagation delay (CPD) is the main concern in this adder. Carry look-ahead and carry select (CS) methods have been suggested to reduce the CPD of adders. A conventional carry select adder (CSLA) is an RCA configuration that generates a pair of sum words and output carry bits corresponding the anticipated input-carry (cin = 0 and 1) and selects one out of each pair for final-sum and final output-carry . A conventional CSLA has less CPD than an RCA, but the design is not attractive since it uses a dual RCA. In the existing designs, logic is optimized without giving any consideration to the data dependence. In this paper, we prepared an analysis on logic operations occupied in conventional and BEC-based CSLAs to study the data dependence and to identify redundant logic operations. Based on this study, we have planned a new logic formulation for the CSLA. The major contribution in this paper is logic formulation based on data dependence and optimized carry generator (CG) and carry select unit Based on the proposed logic formulation, we have found a capable logic design for CSLA. Due to better logic units, the projected CSLA involves significantly less ADP than the existing CSLAs. We have shown that the SQRT-CSLA using the proposed CSLA design involves nearly 32% less ADP than that of the corresponding SQRT-CSLA.

IJARCCE - Computer and Communication Engineering

The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum . However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input , then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption. .

IJARCCE - Computer and Communication Engineering

DESIGN of power-efficient and high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The Carry select adder (CSLA) is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum . However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input , then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption..

제한된 범위의 Signed-Digit Number 인코딩을 이용한 병렬 십진 곱셈기 설계

본 논문에서는 제한된 범위의 Signed-Digit number 인코딩과 축약 단계를 이용한 고정소수점 병렬 십진 곱셈기를 제안한다. 제안한 병렬 십진 곱셈기는 승수와 피승수를 제한된 범위의 SD number로 인코딩하여 캐리 전달 지연 없이 빠르게 부분곱을 생성한다. 인코딩에 사용하는 숫자의 범위를 줄임으로써 SD number 다중 피연산자 덧셈의 한번에 연산 가능한 피연산자의 개수가 늘어나게 되고, 이에 따라 부분곱 축약 단계의 연산을 빠르게 수행 할 수 있다. 제안한 병렬 십진 곱셈기의 성능 평가를 위해 Design Compiler에서 SMIC사의 180nm CMOS 공정 라이브러리를 이용하여 합성한 결과 기존의 Signed-Digit number를 이용한 병렬 십진 곱셈기보다 전체 지연시간은 4.3%, 전체 면적은 5.3% 감소함을 확인 하였다. 전체 지연시간 및 면적에서 부분곱 축약 단계가 차지하는 비중이 가장 크므로 부분곱 생성 단계에서 약간의 지연시간 및 면적 증가가 있음에도 불구하고 전체 지연시간과 면적이 감소하는 결과를 얻을 수 있다.

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier

In binary number system carry is a major problem in arithmetical operation. We have to suffer O(n) carry propagation delay in n-bit binary operation. To overcome this problem signed digit is required for carry free arithmetical operation. Further, literature reviews suggest that multi-valued logic (MVL) would be a better choice to address the problem of developing faster chips for performing faster computational operation. Quaternary Signed Digit (QSD) have a major contribution in higher radix (=4) carry free arithmetical operation. For digital implementation, the signed digit quaternary numbers are represented using 3-bit 2's compliment notation. In this paper, a simple and new technique of binary (2's compliment) to QSD conversion is proposed and described. Well-known operational amplifier (OPAMP) based digital to analog converter circuit is also given to verify the above technique.