Carry Lookahead Adder Research Articles

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Logic Optimization, Complex Cell Design, and Retiming of Single Flux Quantum Circuits

Single flux quantum (SFQ) technology has emerged as a promising beyond-CMOS technology with Josephson junctions (JJs) as active devices in a superconducting circuit. In this paper, we (i) describe the algorithms and the methodology we used to synthesize a synchronous SFQ circuit using a CMOS logic synthesis tool by adding new features to the tool and by modifying the existing features; (ii) introduce the concept of two kinds of complex cells: (a) stand-alone cells and (b) interconnected cells along with the advantage gained by these complex cells through the results of synthesized SFQ netlists. Design of stand-alone complex cells presented here includes and and or gates with more-than-two inputs, high-fanout splitters, and “A+BC” cell. Circuits of decoders, multiplexers, and carrylook-ahead adders are synthesized with complex cells, and the advantage in terms of JJ count and latency is presented. We have also investigated the possibility of SFQ cells supporting multiple fanout drive capability by modifying the input/output interfaces of SFQ standard cells. In this direction, an algorithm to modify the input interface of a cell so that it can be driven along with similar cells by a single splitter output is presented along with the results for a simple clock-distribution line with multiple-fanout capability.

Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method

Reliability is one of the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques have been applied to logic circuits to resist random noise when operating under ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks can be easily mapped onto simple logic circuits, it becomes difficult when the circuits are large and complex. In this paper, we present a general coding-based partial MRF (CPMRF) method for multi-logic operations in one basic unit, which is referred to as a CPMRF pair. A CPMRF pair saves circuit area by sharing a common MRF network. It also inherits noise immunity from the MRF theory while obtaining noise immunity from the coding structure as a combination of robust “1s” and “0s.” The resulting architectures become more cost effective than conventional ones. To validate the performance of our proof-of-concept design, we fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM 130-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20% improvement while occupying 37.7% less area and reducing power consumption by 93% compared with the master-and-slave MRF CLA design.

Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

Improved Designs for All-Optical Adder Circuit Using Mach–Zehnder Interferometers (MZI) Based Optical Components

Since last decade, optical computing has emerged as one of the promising computing paradigm in the field of ultra-fast computations and the recent advancements of fabrication technology in photonic industry has further boosted research interests to investigate in this field. In this conjuncture, strategies for designing efficient optical circuits bear much significance toward building cost efficient logic circuits. Not only synthesis schemes but manual designs for logic components are found very effective in way to produce optimal designs. In this work, we present the optical domain designs of an important logic module of ALU—adder circuit. Not only we have made the adder circuit optical domain supporting one but also we have ensured that the designs are optimized too. Here we have worked with two types of adder circuits Carry-Lookahead Adder and Carry-Skip Adder. All the designs are made using Mach–Zehnder interferometers based optical components and interconnect. For both the adder types, two different designs are shown and in each of these designs both the circuit cost parameters and response time is improved. Design overhead and hardware complexities for all the circuits are computed and have compared with related work’s design, where we have found that our designs are having less delay and cost efficient compared to the existing ones.

Delay, Power performance of 8-Bit ALU Using Carry Look-Ahead Adder with High Vt Cell

Delay, Power performance of 8-Bit ALU Using Carry Look-Ahead Adder with High Vt Cell

Variable Latency approach in VLSI adder Implemented to Reduce Area and Power

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

Design of high speed low power optimized square root BK adder

Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.

Dual Recycled Charge Power Gating For Retaining Data and Saving Leakage

Objectives: To innovate power gating technique which is used to recycle charge lost at moment from active to sleep mode by both PMOS header and NMOS footer. Methods: Three 32-bit Carry Look Ahead (CLA) adder circuits and ISCAS-85 benchmark circuits are compared in retention mode including the conventional power gating, single recycled charge power gating, dual recycled charge power gating in term of the power consumption using the 45 nm Predictive Technology Model. A fair timing comparison also is considered in this work. Findings: This proposed 32-bit CLA adder can reduce the standby leakage power consumption up to 60% and 53% in short and long sleep time, respectively, compared to the conventional power gating. Compared to the single recycled charge, the proposed saves up to 25% in short sleep time and 44% in long sleep time. The proposed 32-bit CLA adder is simpler in controlling the circuit in active mode and retention mode. The ISCAS-85 benchmark circuits are also applied to make conclusion in term of saving leakage power consumption. Application: This proposed leakage reduction technique is promising candidate for optimizing more leakage dissipation in digital circuits. Keywords: Charge Recycling, CLA Adder, Leakage Current, Low Power, Power Gating

An output node split CMOS logic for high-performance and large capacitive-load driving scenarios

In this paper, a new logic with split pull-up (PUN) and pull-down (PDN) networks of static CMOS is presented. The isolation is performed through a push-pull stage and an inner-feedback-interface. This causes two separated outputs of PUN/PDN to have the same voltage in identical evaluating points. Therefore, delay of proposed logic is less than CMOS. Maximum allowable load capacitance of proposed logic is increased. Adaptive-Body-Biasing (ABB) is used during the run-time to change the transistor's effective-threshold-voltage in tradeoff for power and delay. To show the effectiveness of the new logic, an 8-bit Ripple-Carry Adder (RCA), an 8-bit Wallace multiplier and a 16-bit Carry-Look-Ahead Adder (CLA) are implemented and evaluated against, pseudo-static [1] and static CMOS logics on 65 nm standard CMOS technology. Simulations show that proposed logic is 15 and 35% faster than CMOS and pseudo-static, respectively. The proposed logic comes with 28% speedup over CMOS in low-voltage region due to fewer series stages between supply voltage and ground nodes.

Comparative evaluation of quasi-delay-insensitive asynchronous adders corresponding to return-to-zero and return-to-one handshaking

This article makes a comparative evaluation of quasi-delay-insensitive (QDI) asynchronous adders, realized using the delay-insensitive dual-rail code, which adhere to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshake protocols. The QDI adders realized correspond to the following adder architectures: i) ripple carry adder, ii) carry lookahead adder, and iii) carry select adder. The QDI adders correspond to three different timing regimes viz. strong-indication, weak-indication, and early output. They are physically implemented using a 32/28nm CMOS process. The comparative evaluation shows that, overall, QDI adders which correspond to the 4-phase RTO handshake protocol are better than the QDI adder counterparts which correspond to the 4-phase RTZ handshake protocol in terms of latency, area, and average power dissipation.

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

A high-accuracy approximate adder with correct sign calculation

Conventional precise adders take long delay and large power consumption to obtain accurate results. Exploiting the error tolerance of some applications such as multimedia, image processing, and machine learning, a number of recent works proposed to design approximate adders that generate inaccurate results occasionally in exchange for reduction in delay and power consumption. However, most of the existing approximate adders have a large relative error. Besides, when applied to 2's complement signed addition, they sometimes generate a wrong sign bit. In this paper, we propose a novel approximate adder that exploits the generate signals for carry speculation. Furthermore, we introduce a low-overhead module to reduce the relative error and a sign correction module to fix the sign error. Compared to the conventional ripple carry adder and carry-lookahead adder, our adder with block size of 4 reduces power-delay product by 66% and 32%, respectively, for a 32-bit addition. Compared to the existing approximate adders, our adder significantly reduces the maximal relative error and ensures correct sign calculation with comparable area, delay, and power consumption. We further tested the performance of our adders with and without the sign error correction module in three real applications, mean filter, edge detection, and k-means clustering. The experimental results demonstrated the importance of reducing the relative error and ensuring the correct sign calculation for 2's complement signed additions. The outputs produced using our adder with the sign error correction module are very close to those produced using accurate adder.

Reduced Complexity Wallace Tree Mulplier and Enhanced Carry Look-Ahead Adder for Digital FIR Filter

Improvement of Digital FIR filter is vital role in the field of Digital SignalProcessing in order to reduce the area, delay and power. MAC (Multiplication andAccumulation) unit of Finite Impulse Response (FIR) filter has been designed using efficientMultiplier and adder circuits for Optimized APT (Area, Power and Timing) product. In thispaper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially,full adder and half adder structures are shrunk down by reducing number of gates. This compactFull adder and half adder structures are incorporated into reduced Wallace Multiplier andimproved Carry look-ahead Adder. Reduced Wallace tree multiplier and enhanced carry lookaheadadder for digital FIR filter has been proposed in this paper. The proposed 16-bit Carrylook-ahead adder has been improved. Consequently the delay of enhanced Carry look aheadAdder is reduced. Generation of carry output is performed using number of OR gates in asequential manner. All these enhanced architectures are incorporated into the Digital FIR Filterto reduce the area, delay and power utilization. Simulation results are done by using Modelsim6.3C and synthesized by Xilinx ISE 10.1i design tool.

A Novel Nanometric Parity-Preserving Reversible Carry-Lookahead Adder

ABSTRACTDuring recent years, reversible logic received important attention in cryptography, optical processing, quantum computing, and nanotechnology. Among the reversible computation units, the adder unit is considered the most fundamental computation unit to build a quantum computing system. Due to its low latency, the reversible carry-lookahead adder is mostly used and considered. Parity preserving is also one of the oldest methods for error recognition in digital systems. In this article, we offer new proposals for the nanometric parity-preserving reversible 2-bit carry-lookahead adder. Compared with previous designs, we will demonstrate that our designs would be optimal in the number of garbage outputs, constant inputs, and quantum costs. In order to design circuits at a higher level, we also offer new proposals for the nanometric parity-preserving reversible 4-bit carry-lookahead adder. Since previous proposals that were presented as 4-bit did not have the reversible parity-preserving property, we proceeded with our research.

Multiplication With $m$ :2 and $m$ :3 Compressors—A Comparative Review

Compressors are widely used in multipliers to accumulate and reduce partial products in a parallel manner. This paper conducts a comparative review for high-order m:2 and m:3 compressors within a 16-bit × 16-bit multiplier cell as a benchmark. Furthermore, some of the compressors are slightly modified with the aim of reducing interconnections and logical gates. Four well-known adders are also employed to perform the final addition of partial products. They are ripple-carry adder, carry-lookahead adder (CLA), carry-bypass adder, and carry-select adder. These adders are initially demonstrated by a sequence of unmodified identical blocks. Then, they are simplified in order to decrease hardware components. Their simplification and the use of reduced compressors lead to high speed and considerable power and area savings. Synthesizable structural VHDL code is used to simulate and implement different multipliers. Our investigations show that the design with the reduced m:2 compressors and multilevel CLA is the most efficient multiplier. This paper also includes further comparisons with multipliers containing other structures and arrangements.

Carbon nanotube FET‐based low‐delay and low‐power multi‐digit adder designs

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.

ENGLISH

Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer.

Minimization of Area and Power in Digital System Design for Digital Combinational Circuits

This paper proposes enhanced parallel adder architectures with low power and reduced area. It includes, design of three different parallel adders such as Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Select Adder (CSA). All three adders are designed in Gate Diffusion Interface (GDI) technique as well as traditional CMOS method. Adder is a basic common combinational digital circuit. Adders are important components in signal processing, image and video processing applications. So it is essential to have compact, low power adder design for these application fields. GDI based digital system design offers reduction in power consumption and area over head. When compared to traditional CMOS based design, GDI uses very less transistor to implement a function. The GDI and CMOS methods are taken in to account for the comparison of design parameters such as design layout, node to node delay, total power dissipation and speed of operation. All three parallel adders are designed in traditional CMOS as well as GDI method. The simulations are done using Microwind2 and DSCH2 analysis software tools and the results between those two types are listed below. This proposed adder circuits can be used in all high speed multipliers and filter designs where low power and reduced area is a major concern.

Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits

Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.