Carrier Tunneling Research Articles

Effects of barrier thickness on carrier non-radiative relaxation process in InGaAs/GaAsP superlattice solar cells by piezoelectric photothermal and surface photovoltage spectroscopies

We investigated the carrier non-radiative relaxation process of InGaAs/GaAsP superlattice (SL) solar cells with different barrier thicknesses by combining piezoelectric photothermal (PPT) and surface photovoltage (SPV) measurements. The former technique detected heat generated by non-radiative relaxation and the latter detected the surface potential change induced by the carrier accumulation. Although the mechanisms of these measurements were different, corresponding signals of the transition between the quantum levels were observed in both spectra. The SPV signal intensities were independent of the barrier thicknesses. The carrier tunneling process functioned poorly under open-circuit conditions. Conversely, the PPT signal intensities increased with decreasing barrier thickness. We experimentally demonstrated that the non-radiative relaxation component increased as the barrier thicknesses decreased owing to the lattice relaxation at interfaces between the quantum well and barrier layers. We concluded that the non-radiative relaxation process in the SL structure must be directly evaluated to improve the solar cell performance.

Photocurrent generation under forward bias with interfacial tunneling of carrier at pentacene/F16CuPc heterojunction photodetector

Fabrication of a bilayer organic photodetector (OPD) based on pentacene and copper–hexadecafluoro-phthalocyanine (F16CuPc) has been done employing thermal evaporation method. The photo-response characteristics of OPD have been investigated under illumination of light having different wavelengths. Absorption from 300 nm to 900 nm has been observed for this series of OPD, obtained after annealing at different temperatures. Experimental results on this series of OPD reveal quite symmetric current density – voltage (J-V) characteristics both at forward and reverse bias condition. We have attributed such symmetric J-V response to efficient electron tunneling between highest occupied molecular orbital of pentacene to lowest unoccupied molecular orbital of F16CuPc. This is being confirmed further using Fowler-Nordheim tunneling model. Atomic force microscopy (AFM) and field emission scanning electron microscopy (FE-SEM) images indicate degradation of device responsivity with increase in annealing temperature. The relatively higher responsivity (0.0029 A/W) with respect to available reports indicate that the pentacene/F16CuPc heterojunction will be one of the promising materials for optoelectronics mixer and photodetector applications below 850 nm.

Understanding Interlayer Contact Conductance in Twisted Bilayer Graphene.

Bilayer or few-layer 2D materials showing novel electrical properties in electronic device applications have aroused increasing interest in recent years. Obtaining a comprehensive understanding of interlayer contact conductance still remains a challenge, but is significant for improving the performance of bilayer or few-layer 2D electronic devices. Here, conductive atomic force microscope (C-AFM) experiments are reported to explore the interlayer contact conductance between bilayer graphene (BLG) with various twisted stacking structures fabricated by the chemical vapor deposition (CVD) method. The current maps show that the interlayer contact conductance between BLG strongly depends on the twist angle. The interlayer contact conductance of 0° AB-stacking bilayer graphene (AB-BLG) is ≈4 times as large as that of 30° twisted bilayer graphene (t-BLG), which indicates that the twist angle-dependent interlayer contact conductance originates from the coupling-decoupling transitions. Moreover, the moiré superlattice-level current images of t-BLG show modulations of local interlayer contact conductance. Density functional theory calculations together with a theoretical model reproduce the C-AFM current map and show that the modulation is mainly attributed to the overall contribution of local interfacial carrier density and tunneling barrier.

Electric field and oxygen concentration-dependent transport properties of nano-graphene oxide

Electrical transport properties of the nano-graphene oxide were investigated by measuring current-voltage characteristics in the wide temperature range of 15 K∼450 K. The n-GO is composed of nanometer-sized intact graphene-like sp2 domains embedded in the sp3 matrix which acts as a charge transport barrier between the highly conductive sp2 domains. The oxygen in the n-GO has the concentration of 4.43 at% in the form of oxygen functional groups. Below the conduction band, four discontinuous localized states with the activation energies of 1.92 meV, 3.27 meV, 5.54 meV, and 6.58 meV were observed. These activation energies decrease with decreasing oxygen concentration and increasing external electric field in the n-GO material. Moreover, we found that the direct tunneling of charge carrier through the sp3 barrier was a dominant transport mechanism for the n-GO material. Also, unlike the activation energy of charge carrier, the transport barrier was independent of both the concentration of the oxygen functional groups and external electric field. The transport barrier was mainly determined by insulation property of the sp3 structure.

Electron pairing in the pseudogap state revealed by shot noise in copper oxide junctions.

In the quest to understand high-temperature superconductivity in copper oxides, debate has been focused on the pseudogap-a partial energy gap that opens over portions of the Fermi surface in the 'normal' state above the bulk critical temperature1. The pseudogap has been attributed to precursor superconductivity, to the existence of preformed pairs and to competing orders such as charge-density waves1-4. A direct determination of the charge of carriers as a function of temperature and bias could help resolve among these alternatives. Here we report measurements of the shot noise of tunnelling current in high-quality La2-xSrxCuO4/La2CuO4/La2-xSrxCuO4 (LSCO/LCO/LSCO) heterostructures fabricated using atomic layer-by-layer molecular beam epitaxy at several doping levels. The data delineate three distinct regions in the bias voltage-temperature space. Well outside the superconducting gap region, the shot noise agrees quantitatively with independent tunnelling of individual charge carriers. Deep within the superconducting gap, shot noise is greatly enhanced, reminiscent of multiple Andreev reflections5-7. Above the critical temperature and extending to biases much larger than the superconducting gap, there is a broad region in which the noise substantially exceeds theoretical expectations for single-charge tunnelling, indicating pairing of charge carriers. These pairs are detectable deep into the pseudogap region of temperature and bias. The presence of these pairs constrains current models of the pseudogap and broken symmetry states, whilephase fluctuations limit the domain of superconductivity.

Separation and Quantum Tunneling of Photo-generated Carriers Using a Tribo-Induced Field

Tribo-induced potential at a metal-insulator-semiconductor sliding junction results in very high interfacial electric field E (∼107–108 V/m). Such fields are used to separate photo-generated electron-hole pairs that transport through the junction via quantum tunneling. We show that this phenomenon can generate direct current with high current density J. The strong synergetic effect between the photo-excitation and the interfacial electronic excitation at the MIS sliding contact boosts the photocurrent output in Si-based Schottky solar cell by ∼50 times and the triboelectric power output by ∼28 times. Charge relaxation dynamics calculations agree well with conductive atomic force microscopy results and show the coupling effect between the photo- and the tribo-induced electric fields. Experimental observation of the tribo-photovoltaic effect provides new fundamental understanding of electromechanical coupling, and thus offers a new direction for future solar-mechanical energy co-harvesting.

Carrier escape mechanism in laterally correlated InAs sub-monolayer quantum dots using temperature dependent photoluminescence

We have quantitatively investigated relative effects of photo-carrier escape mechanism upon the quenching of photoluminescence with temperature in an ensemble of embedded InAs sub-monolayer (SML) quantum dots by varying InAs SML coverage from 0.4 ML to 0.8 ML. The mutual interplay of carrier recombination and tunneling throughout the laterally coupled quantum dots for different InAs coverage have been established to determine the temperature dependent photoluminescence (TDPL) spectra. The respective characteristic life times were extracted from the individual TDPL spectra by fitting them with model carrier rate equation. The consequent enhancement of inter-dot tunnel strength with respect to the carrier recombination rate with increasing InAs coverage has been marked out to be responsible for sustainable photoluminescence efficiency at higher temperature. Enhancement of tunneling rate with increasing InAs SML coverage has been physically described as consequence of reduced average inter-dot lateral separation as estimated from grazing incidence small angle x-ray scattering (GISAXS) measurement. Moreover, we have observed the anomalous decrease of spectral linewidth with temperature which can also be described as a consequence of the tunnel induced faster inter-dot carrier transfer at higher sub-monolayer coverage. The absence of any wetting layer in SML QD resulted in speeding up of carrier transfer through inter-dot tunneling pathways with tunnel time as low as 350 ps. This is significantly faster than the conventional InAs/GaAs SK QDs with tunnel time of 1328 ps.

Tunneling of photon-generated carrier in the interface barrier induced resistive switching memory behaviour

The resistive switching effect is a great physical phenomenon that the resistance of a material can be reversibly changed by applying an electric pulse, which is useful to constructing the nonvolatile resistance random access memory (RRAM) in the next generation of memory system. In this work, a sandwich structure (ITO/WO3/AZO) was prepared by using WO3 film (∼300 nm) as the dielectric layer meanwhile indium tin oxide (ITO) as the top electrode and aluminium-doped zinc oxide (AZO) as the bottom electrode. An enhanced resistive switching memory behavior was observed in the sample processed by light-illumination. Furthermore, the set voltage (Vset) and reset voltage (Vreset) are increased but the HRS/LRS resistance ratio is decreased with the increasing of illumination time for 600 °C annealed sample. Through further analysis, a physical model on the tunneling of photon-generated carrier in the Schottky barrier layer driven by electric pulse is proposed to explain the enhanced resistive switching memory behavior. The suggested mechanism is highly pivotal for the resistive switching phenomenon to be properly applied in the nonvolatile RRAM device.

InAs/GaSb superlattice interband cascade light emitting diodes with high output power and high wall-plug efficiency

In this work, 2-stage and 5-stage mid-infrared superlattice interband cascade light emitting diodes (ICLEDs) were fabricated and studied at different temperatures. The ICLEDs were composed of InAs/GaAsSb active regions, InAs/AlAsSb injection regions, and GaAsSb/AlAsSb tunneling regions. The devices exhibited high output power and very low series resistance, indicating efficient carrier blocking and tunneling in the designed structure. Radiances of 0.73 W/cm2 sr and 0.38 W/cm2 sr were achieved at 300 K for the 5-stage and 2-stage ICLEDs, respectively. With an output power of 3.56 mW, the wall-plug efficiency of the 5-stage ICLED reached 0.5% at 80 K, under an injection current of 350 mA. The efficiency was largely maintained in the same range with increasing current injection. The results showed that ICLEDs have great potential for mid-infrared light emitting diode applications requiring large output power and high wall-plug efficiency.

Transport and storage dynamics of 30% In-rich InGaN/GaN MQW LED p–i–n structure

DC and AC electrical characteristics of an InGaN/GaN multi-quantum well light emitting diode based on PIN structures were investigated through temperature-dependent current–voltage (I--T) and admittance-temperature-frequency (Y-T-) measurements within 80–375 K temperature interval. Multi-step tunneling was discerned as a carrier conduction mechanism for whole reverse and small forward biases at the high-temperature side in the studied temperature interval while hopping conduction at the low side. Electron and hole as the tunneling carriers were identified through activation energy, 110 meV and 60 meV respectively. The values were determined from I--T/C-T- measurements in conjunction with conductance of quantum well itself and consisted with the reported activation energy; 120–220 meV for electrons, 50–80 meV for holes.

Rectifying Characteristics of Thermally Treated Mo/SiC Schottky Contact

The rectifying characteristics of a Mo/SiC Schottky contact fabricated by facing targets sputtering system were investigated through current–voltage measurement. The Schottky diode parameters were extracted from the forward current–voltage characteristic curve by the Cheung and Cheung method and the Norde method. The as-deposited Mo/SiC Schottky contacts possessed Schottky barrier heights of 1.17 and 1.22 eV, respectively. The Schottky barrier heights of the diodes were decreased to 1.01 and 0.91 eV after annealing at 400 °C for 30 min. The ideality factor was increased from 1.14 and 1.08 to 1.51 and 1.41, respectively. This implies the presence of non-ideal behaviors due to a current transport mechanism other than ideal thermionic emission, and the non-ideal behaviors increased as a result of excessive thermal annealing. In contrast, only a negligible change was observed in the crystallographic characteristics. This result suggests that the reason for the deviation from the ideal rectifying characteristics of the Mo/SiC Schottky contact through the annealing process was the variation in the current transport mechanism, including recombination, tunneling, and/or minority carrier injection.

Studies on Pitting Corrosion of Al-Cu-Li Alloys Part III: Passivation Kinetics of AA2098-T851 Based on the Point Defect Model.

In this paper, the passivation kinetics of AA2098–T851 was investigated by a fundamental theoretical interpretation of experimental results based on the mixed potential model (MPM). The steady state passive layer formed on the AA2098–T851 in NaHCO3 solution in a CO2 atmosphere upon potentiostatic stepping in the anodic direction followed by stepping in the opposite direction was explored. Potentials were selected in a way that both anodic passive dissolution of the metal and hydrogen evolution reaction (HER) occur, thereby requiring the MPM for interpretation. Optimization of the MPM on the experimental electrochemical impedance spectroscopy (EIS) data measured after each potentiostatic step revealed the important role of the migration of Al interstitials in determining the kinetics of passive layer formation and dissolution. More importantly, it is shown that the inequalities of the kinetics of formation and dissolution of the passive layer as observed in opposite potential stepping directions lead to the irreversibility of the passivation process. Finally, by considering the Butler–Volmer (B–V) equation for the cathodic reaction (HER) in the MPM, and assuming the quantum mechanical tunneling of the charge carriers across the barrier layer of the passive film, it was shown that the HER was primarily controlled by the slow electrochemical discharge of protons at the barrier layer/solution (outer layer) interface.

Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

The carrier transport and tunneling mechanisms in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) with different dielectric layers is investigated using a simple two-dimensional analytical model, revealing good agreement with drift–diffusion and hydrodynamic models at lower gate voltages. The model is utilized to optimize the MOSFET performance by minimizing the carrier leakage and improving the gate control on the carrier transport through the channel, which can be determined by the gate-to-drain capacitance ratio. It is well known that thicker physical layers of high-k dielectrics can be used to reduce the gate tunneling current without compromising the gate controllability over the channel conduction, by providing the same equivalent oxide thickness as SiO2. However, use of a dielectric layer with a lower conduction-band offset (CBO) in a Si MOSFET can result in appreciable tunneling through the gate, as shown in our computational results for the TiO2 layer. In this study, we obtain an optimized thickness of 10 A for the La2O3 dielectric layer, which results in a minimum leakage current via tunneling and a maximum gate-to-drain capacitance ratio due to its high dielectric constant and CBO. Such devices could be applicable in analog amplifier circuits due to their high intrinsic gain and lower “on” and “off” static power dissipation. The analysis of this device in a digital circuit also shows a higher Ion/Ioff ratio with the least drain-induced barrier lowering effect. The results of this study thus predict the suitability of this MOSFET for use in low-power devices and logic circuits.

Performance analysis of nanoscale double gate strained silicon MOSFET with high k dielectric layers

This study presents a theoretical model to describe the combined characteristics of strained silicon nanoscale double gate MOSFET along with high k dielectric layer. Although a well- tempered MOSFET with strong gate electrostatics can be devised using high k gate material, lower conduction band offset (CBO) over silicon results in leakage and subsequent static power dissipation. The study shows that this effect can reduce the Ion/Ioff ratio to 2 × 102 with 2 nm thick TiO2 dielectric layer (k = 60) along with mobility degradation. Incorporating the effects of strained silicon and high k dielectrics in MOSFETs exhibits bandstructure alteration and increase in CBO. This inhibits carrier tunnelling causing leakage with restoration of Ion/Ioff ratio to 4.5 × 106. The mobility can also be improved along with the maintenance of effective gate electrostatics. Thus the study illustrates the possibility of designing the nanoscale MOS devices with all the essential characteristics without trade-off over other performance parameters.

Modeling Atomic-Scale Electrical Contact Quality Across Two-Dimensional Interfaces.

Contacting interfaces with physical isolation and weak interactions usually act as barriers for electrical conduction. The electrical contact conductance across interfaces has long been correlated with the true contact area or the "contact quantity". Much of the physical understanding of the interfacial electrical contact quality was primarily based on Landauer's theory or Richardson formulation. However, a quantitative model directly connecting contact conductance to interfacial atomistic structures still remains absent. Here, we measure the atomic-scale local electrical contact conductance instead of local electronic surface states in graphene/Ru(0001) superstructure, via atomically resolved conductive atomic force microscopy. By defining the "quality" of individual atom-atom contact as the carrier tunneling probability along the interatomic electron transport pathways, we establish a relationship between the atomic-scale contact quality and local interfacial atomistic structure. This real-space model unravels the atomic-level spatial modulation of contact conductance, and the twist angle-dependent interlayer conductance between misoriented graphene layers.

Environmental factors controlled resistive switching memory behavior based on BiFeO3/Cu2ZnSnSe4 heterojunction

Abstract With the memory device is required to be widely used in more complex environment, the exploration of new memory device have become a focus of research. Herein, a resistive switching memory device based on BiFeO3(BFO)/Cu2ZnSnSe4(CZTSe) heterostructure is demonstrated, further the resistive switching characteristics of as-prepared device are characterized under different testing environments, suggesting an environmental factors controlled memory behavior is observed. Finally, we propose a new mechanism to explain the resistive switching effect based on the tunneling of interfacial carriers induced filament formation. This work demonstrates that the resistive switching memory device constructed by advanced semiconductor heterostructure display superior application value because they can work in complex environments.

AlxTe1−x selector with high ovonic threshold switching performance for memory crossbar arrays

We report the fabrication of a bidirectional selector based on threshold switching (TS) material AlxTe1−x. By modulating the composition and the thickness of the AlxTe1−x film layer, an optimized bidirectional selector with the advantages of being electroforming-free, with sufficient operating current (1 mA), satisfactory selectivity (ca. 5.9 × 103), appropriately small threshold voltage (ca. ±0.7 V), and excellent switching uniformity was fabricated. The trap-limited conduction model was employed to explain the TS characteristics of the W/AlxTe1−x/W device. The application of a high electric field to the devices is considered to induce the tunneling of the high-electric field-derived carriers from deep traps to shallow traps, switching the device to the on-state.

Ultraviolet polarized light emitting and detecting dual-functioning device based on nonpolar n-ZnO/i-ZnO/p-AlGaN heterojunction.

We report on the demonstration of a 386nm light emission and detection dual-functioning device based on nonpolar a-plane n-ZnO/i-ZnO/p-Al0.1Ga0.9N heterojunction under both forward and reverse bias. The electroluminescence intensity under reverse bias is significantly stronger than that under forward bias, facilitated by carrier tunneling when the valence band of p-AlGaN aligns with the conduction band of i-ZnO under reverse bias. Also amid reverse bias, the photodetection was observed and applied in a duplex optical communication device. Optical polarization of the light emission is studied for potential polarization-sensitive device applications. The proposed device provides an important pathway for the multifunctional devices operating in a UV spectrum.

Structural dependent, dielectric and conduction analysis of CdSe based quantum dots

Nowadays, the effect of temperature on nanocrystal’s dielectric has become a routine study while their structural effects on dielectric properties, lacks the attention of researchers. The correlation of different shell arrangement on dielectric enhancement in CdSe based quantum dots, is addressed in this letter. Detrimental impact of surface defects on dielectric properties of quantum dots is investigated and shown that surface defects of bare core increases dielectric loss, dissipation factor and decreases conductivity of the quantum dots. Dielectric properties of quantum dots is evaluated after deposition of different shells and multishells. It is observed that loss factor is declined in core/shell(multishell) quantum dots due to passivation of surface defects and consequently ease in charge carrier tunneling. Higher conductivity of the core/shell and multishell structures has also been demonstrated here. Structural and optical investigation of the quantum dots after shell deposition is also considered.

Understanding the electrostatics of top-electrode vertical quantized Si nanowire metal–insulator–semiconductor (MIS) structures for future nanoelectronic applications

In this paper, a comprehensive analysis of the electrostatics of top-electrode vertically aligned quantized Si nanowire metal–insulator–semiconductor (MIS) structure is performed by formulating a self-consistent analytical model with simultaneous solution of Schrodinger and Poisson equations. The impact of high-k dielectrics on the electrostatic control of such quantized nanowire MIS devices is studied in detail. The electrostatic control is observed to degrade significantly for such high-k insulators with identical equivalent oxide thickness (EOT) due to the nonlinear dependence between dielectric constant and EOT in quantized nanowire MIS devices. The distribution of 3D confined charges along the nanowire is primarily governed by the generated quantum states which are a nonlinear function of the applied voltage. The electrostatic integrity of such device is investigated in terms of simultaneously maintaining the electrostatic control and reduction in carrier tunneling probability. In this context, the impact of several controlling parameters such as applied voltage, barrier height of the insulator/semiconductor junction, carrier effective mass of the insulator and nanowire diameter on tunneling probability is examined. The results suggest insulator effective mass (high-m*) to be the more significant parameter for maintaining electrostatic integrity than its dielectric constant (high-k) in quantized nanowire top-electrode MIS devices.