As advanced CMOS technology scaling goes beyond 7nm node, contact resistivity becomes an important factor influencing device performance. Approaches to reduce contact resistivity involve advanced doping techniques that yield very high degree of dopant activation at the semiconductor layers comprising the source and drain regions. These approaches include in-situ heavily doped epi layers and ion implantation followed by advanced annealing techniques. Irrespective of the approach used in wafer processing, accurate analysis of dopant activation within the top few nanometers of the surface is critical to understanding the effectiveness of such processes on improving contact resistivity. Similarly, correlation of mobility depth profile to defectivity in the layers helps one to understand how process variables may affect the ultimate electrical properties.Differential Hall Effect Metrology (DHEM) is the only method that can provide mobility and active dopant depth profiles through semiconductor layers at sub-nm resolution. The method employs electrochemical means of reducing the electrically active thickness of a semiconductor film and determining the sheet resistance and mobility of the thinned down layer using Van der Pauw/Hall effect type measurements [1].In this work we characterized an ion implantation/annealing process cycle using DHEM and TEM studies. The sample was a p-type Si wafer ion implanted with P (10keV, 2E15cm-2). After implantation, the wafer was coated with positive photoresist, exposed, and developed in order to define a cross-shaped Van der Pauw structure. After formation of the DHEM test patterns using dry etching, wafer pieces were processed by rapid thermal anneal (RTA) at 750 ºC, 850 ºC, and 950ºC in nitrogen ambient for 30 seconds. After annealing, samples were subjected to a negative photoresist process in order to open contact windows. After the exposure and development, native oxide was removed from the contact windows and metallic contacts were evaporated. Depth profiles of resistivity, mobility, and carrier concentration were measured by DHEM using an ALPro™ 50 electrical profiling tool.Fig. 1 shows the cross-sectional TEM images of the P ion implanted samples after annealing at (a) 750ºC, (b) 850ºC, and (c) 950ºC. As can be seen in Fig 1(a) the end of range (EOR) defects are located at approximately 26-30 nm from the surface in this sample. The 750ºC RTA process did not adequately resolve these defects. However, it is clear from the TEMs that defects at the original location of the a-Si/c-Si interface decreased gradually when the samples were annealed at increasing RTA temperatures (see Fig. 1(b−c)), when crystallinity of the ion implanted top layer also improved.The depth profiles of active carrier concentration after RTA process are given in Fig.2(a). Three regions can be discussed in these depth profiles. Region 1 is within 15nm of the surface, region 2 is at around 20-30 nm depth, and region 3 is at depths at or larger than 40nm. As can be seen in this figure, higher and higher RTA temperatures result in diffusion of P impurities deeper, and dopant activation at region 3 gets higher and higher as the anneal temperature is increased from 750ºC to 950ºC. As for the region 1, we observe a small decrease in carrier concentration values with higher temperature (from about 3.77E+20 #/cm3 to about 2.95E+20 #/cm3) as the overall active dopant profile becomes more uniform due to diffusion.Figure 2(b) shows the mobility depth profiles of the three samples discussed with reference to Fig. 1 and Fig. 2(a). It is obvious from this figure that the mobility profile is relatively flat within the implantation region (<30nm). Notably the mobility value for the RTA 750ºC sample dips at a depth in the range of 25-30 nm, where Fig. 1(a) shows extensive EOR defectivity. Therefore, the correlation with deteriorated mobility at that region is excellent. It is also clear from the mobility data that as the annealing temperature is raised to 850ºC and then to 950ºC this dip in mobility disappears, suggesting reduction in defects through higher temperature annealing. Deeper region (>40nm) mobility reduces with increasing temperatures because of increased carrier scattering mechanisms as more of the dopant is activated deeper at the elevated temperatures.Through this work we have demonstrated how DHEM technique can be utilized to correlate electrical and physical data obtained from samples subjected to doping processes. At the present time we are extending this work to ultra shallow junction structures and these results will be presented at the conference.
Search from 250 M+ research papersSearch from 250 M+ research papers
Oct 3, 2024
J Kuzmík + 11
Open Access