Carrier Board Research Articles

Implementation of the VMM ASIC in the Scalable Readout System

The Scalable Readout System (SRS) developed by the RD51 collaboration is a versatile and multi-purpose approach, which is used with different front-end chips to transfer data from detectors to computers. Targeting mainly micro-pattern gaseous detectors, the system is also applicable for silicon strip or pad detectors. The most frequently used front-end chip today is the APV25, originally developed for the CMS pixel detector. In the scope of the ATLAS New Small Wheel upgrade, a new front-end chip, the VMM, is developed, which has significantly improved specifications compared to the APV25.We report on the implementation of the VMM in the Scalable Readout System carried out by the RD51 collaboration in the framework of a detector project related to the European Spallation Source ERIC. Due to the hierarchical design of the Scalable Readout System, only specific parts of the readout chain need to be adapted or designed, which is the carrier board for the front-end chip, an adapter card that connects to the common hardware of the system and the firmware for a field programmable gate array. In addition, we have developed dedicated software for slow control, data acquisition and online monitoring. The readout system has been tested in the laboratory and in particle beams and we present results which proof the functioning of the system, even though it is still in a prototype state.

3D Multifunctional Composites Based on Large‐Area Stretchable Circuit with Thermoforming Technology

AbstractFiber‐reinforced polymer composites with integrated intelligence, such as sensors, actuators, and communication capabilities, are desirable as infrastructures for the next generation of “internet of things.” However, the shape mismatch between the 3D composites and a planar electronic circuit causes difficulties in integrating electronic circuit‐based intelligences. Here, an easily scalable approach, by incorporating a large‐area stretchable circuit with thermoforming technology, to fabricate 3D multifunctional composites is reported. The stretchable circuit is first fabricated on a rigid and planar carrier board, then transferred and sandwiched between thermoplastic composites through lamination processes. A thermoforming step shapes the sandwiched and planar structure by heating up the encapsulating polymers beyond their glass transition temperature and pushing them and the circuit against a mold. Using the proposed process, large‐sized composites with integrated matrices of light‐emitting diodes (LEDs) and capacitive sensors are successfully fabricated. A giant (with a size of 0.5 m × 1 m) seven‐segment display is assembled using the fabricated composites with integrated LEDs and capacitive sensors to display 128 symbols. The results demonstrate the potential of the proposed approach as a facile, reproducible, and scalable process for creating 3D multifunctional composites.

60-GHz CMOS Doppler Radar Sensor With Integrated V-Band Power Detector for Clutter Monitoring and Automatic Clutter-Cancellation in Noncontact Vital-Signs Sensing

This paper presents the design of a V-band logarithmic power detector (PD) and the integration with a 60-GHz CMOS vital-signs Doppler radar sensor to be incorporated with a microprocessor control unit (MCU) for fast automatic clutter cancellation. The PD adopts the successive detection logarithmic amplifier (SDLA) topology and achieves a high dynamic range by replacing the limited amplifiers with millimeter-wave (MMW) linear amplifiers. From the measurement results, the PD exhibits a dynamic range and logarithmic errors higher than 35 dB and within ±2 dB from 50 to 62 GHz. The whole integrated radar sensor chip is fabricated by a 90-nm CMOS process with a chip size of 2 mm $\times2.34$ mm and a dc power consuming of 243 mW. The radar chip and a 60-GHz 17-dBi patch-array antenna are integrated by bondwire interconnection on a compact single carrier board for experimental test. By incorporating the MCU to the radar chip board, the fast automatic clutter canceling can achieve more than 25-dB clutter cancellation. Moreover, it shows a successful vital-signs detection for a distance more than 1.2 m.

Integrated Packaging Design of Low-Cost Bondwire Interconnection for 60-GHz CMOS Vital-Signs Radar Sensor Chip With Millimeter-Wave Planar Antenna

This paper presents a compact integration design of a low-cost bondwire-interconnection scheme between a 60-GHz CMOS vital-signs Doppler radar sensor chip and a millimeter-wave patch-array planar antenna (17-dBi gain). The interconnection has the form of an inductance-capacitance-inductance structure configured as a T-matching network. It consists of a short microstrip line as a small capacitance and parallel bondwires as inductance. Open-ended stubs are additionally applied in the design to improve the ground connection at 60 GHz. To enhance the robustness of the impedance-matching bandwidth to withstand possible bonding length variations, additional series and shunt transmission lines are also deployed. The proposed low-cost integrated circuit-to-board interconnection design requires no additional processing (e.g., cavity etching of the carrier board). In the experimental measurement, compared with the radar sensor connected with a 7-dB-loss ${V}$ -band cable to the planar antenna in a previous report, the implemented compact bondwire-interconnected CMOS radar antenna module can enhance the detection range from 75 to at least 105 cm [and potentially up to 120–150 cm if the radar chip output power (0 dBm) is the same as 3 dBm]. This shows the potential facilitation for the incorporation of the 60-GHz radar sensor chip into portable devices for wireless remote physiological monitoring healthcare applications.

An upgrade of the camera focal plane of a SchwarzschildCouder Telescope prototype (pSCT) for the Cherenkov Telescope Array (CTA)

The Cherenkov Telescope Array (CTA) will be the next generation of ground-based observatory of very high energy gamma ray sources. The Italian Institute of Nuclear Physics (INFN) is involved in the R&D effort for the development of a possible solution for one of the Cherenkov photon camera designs, working on replacing the Hamamatsu MPPC S12642-0404PA-50 with more UV sensitive ones from Fondazione Bruno Kessler (FBK). INFN is currently developing the preamplifiers and the carrier boards for the SiPM chips that interface with the mechanics of the camera. To test the feasibility and the performance of SiPM cameras, a focal plane camera prototype module, upgraded with High Density NUV - SiPMs, produced by FBK, with a micro cell of 30 μm x 30 μm and 6 mm x 6 mm area, is being assembled. In this work, we describe the SiPM carrier boards, the assembly process and the qualification tests performed, before and after assembly, on the focal plane modules to qualify the procedures.

Construction and assembly of the wire planes for the MicroBooNE Time Projection Chamber

In this paper we describe how the readout planes for the MicroBooNE Time Projection Chamber were constructed, assembled and installed. We present the individual wire preparation using semi-automatic winding machines and the assembly of wire carrier boards. The details of the wire installation on the detector frame and the tensioning of the wires are given. A strict quality assurance plan ensured the integrity of the readout planes. The different tests performed at all stages of construction and installation provided crucial information to achieve the successful realization of the MicroBooNE wire planes.

ALICE inner tracking system readout electronics prototype testing with the CERN ``Giga Bit Transceiver''

The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to the DAQ. To prototype various aspects of this readout system, an FPGA based carrier board and an associated FMC daughter card containing the CERN Gigabit Transceiver (GBT) chipset have been developed. This contribution describes laboratory and radiation testing results with this prototype board set.

Versatile prototyping platform for Data Processing Boards for CBM experiment

The CBM experiment is one of the experiments prepared at the FAIR Facility in Darmstadt. The Data Processing Boards (DPB) are an important component of the CBM readout chain. Before the final, production versions of DPB may be designed, it is important to create a prototyping platform, to test and select appropriate hardware and firmware solutions. The Kintex based AMC FMC Carrier (AFCK) board is a versatile and open solution fulfilling those requirements, offering configurable high-speed (up to 10 Gbps) connectivity. The paper describes the AFCK hardware, the firmware architecture, and the IP cores developed for different DPB prototyping tasks. Due to its versatility and openness the AFCK may be reused in other experiments.

Evaluation of a commercial AdvancedTCA board management controller solution (IPMC)

The MicroTCA (MTCA) and AdvancedTCA (ATCA) industry standards have been selected as the hardware platform for the upgrade of the electronic systems of some of the experiments at the Large Hadron Collider (LHC) . In this context, the electronics support group for experiments at CERN is running a project to perform technical evaluations of MTCA and ATCA equipment. As part of this activity, a commercial solution for an Intelligent Platform Management Controller (IPMC), an essential component of any ATCA blade design, is being evaluated. We validated the supported IPMC features, checked the interoperability and adapted the reference design for use on an existing ATCA carrier board.

SPIDR: a read-out system for Medipix3 & Timepix3

The realisation of the Timepix3 chip opened the way for new opportunities in research areas such as particle tracking with both semiconductor sensors and gas filled time projection chambers, electron microscopy and imaging mass spectrometry. To exploit the full capability of the Timepix3 chip, Nikhef developed a compact read-out system, called SPIDR that can deal with the high data output of 80 Mhits per chip per second. The main read-out board connects to both 10 Gb Ethernet and 1 Gb Ethernet devices. The latter obviously at a reduced rate. The main board connects to individual chip-carrier boards via a standard FMC connector. The system is designed such that support for other readout chips is foreseen via reprogramming of the FPGA. Besides the Timepix3 chip also the Medipix3 chip is currently supported. Both the main board and the chip carrier boards are cooled, via the housing and a fan to obtain a stable temperature of around 40 ± 0.2 °C for the Timepix3 chips. We will present the system and the results obtained with the LHCb beam telescope at CERN and proton radiography data obtained with a time projection chamber based on GEM technology.

2.5D Smart Objects Using Thermoplastic Stretchable Interconnects

This contribution describes the technology used to produce thermoplastically deformable electronics, based on flexible circuit board technology, to achieve low-cost 2.5D free-form rigid smart objects. These one-time deformable circuits employ a modified version of the previously developed meander-based “polymer-last” technology for dynamically stretchable elastic circuits. This is readily achieved by substituting the dynamically stretchable elastomeric materials (e.g. silicone) with thermoplastic polymers (e.g. polycarbonate). Afterwards the circuit is given its final form using widely available thermoforming techniques, such as vacuum forming, where the material is heated above its glass transition temperature and drawn against a forming tool by a strong vacuum. After cooling down the thermoplastic retains its shape without inducing large internal stresses. The presented method allows for the production of these circuits on a flat substrate, using standard printed circuit board production equipment, with deformation only taking place afterwards; eliminating the need for large investments and reducing the cost of fabrication. Potential advantages over competitive methods are reductions in weight and material usage, decrease of mechanical complexity; lower tooling cost, increased resilience, and a higher degree of manufacturer independence due to adhering to standard industrial practices. This is realized by starting production from a flexible circuit board, manufactured by an industrial supplier using polyimide flexible copper clad laminate, which is attached to a temporary reusable carrier board through means of a silicone based high-temperature pressure sensitive adhesive. Through selective laser structuring the meander and island outlines of the flexible circuit are defined, without causing damage to the carrier board or pressure sensitive adhesive. After removing the residual material the circuit is assembled using high-temperature lead-free solder, made possible by the temporary carrier keeping the circuit in place at these elevated temperatures. The circuit is then transferred into a thermoplastic laminate, which is deformed into its final shape. After demonstrating the need for stretchable electronics for this application, this contribution describes the method used to design, fabricate, and test the first one-time deformable circuits manufactured using the presented technology. Using the initial set of observations a series of preliminary design rules is established, both for the circuit and choice of materials. The feasibility of this manufacturing method was then demonstrated through a small scale production run using lab scale equipment, where a large quantity of high power LEDs was integrated into a one-time deformable device made out of polystyrene and thermoplastic polyurethane. These devices were then tested by exposing them to real world conditions for several days.

The ONSEN Data Reduction System for the Belle II Pixel Detector

We present an FPGA-based online data reduction system for the pixel detector of the future Belle II experiment. The occupancy of the pixel detector is estimated at 3 %. This corresponds to a data output rate of more than 20 GB/s after zero suppression, dominated by background. The Online Selection Nodes (ONSEN) system aims to reduce the background data by a factor of 30. It consists of 33 MicroTCA cards, each equipped with a Xilinx Virtex-5 FPGA and 4 GiB DDR2 RAM. These cards are hosted by 9 AdvancedTCA carrier boards. The ONSEN system buffers the entire output data from the pixel detector for up to 5 seconds. During this time, the Belle II high-level trigger PC farm performs an online event reconstruction, using data from the other Belle II subdetectors. It extrapolates reconstructed tracks to the layers of the pixel detector and defines regions of interest around the intercepts. Based on this information, the ONSEN system discards all pixels not inside a region of interest before sending the remaining hits to the event builder system. During a beam test with one layer of the pixel detector and four layers of the surrounding silicon strip detector, including a scaled-down version of the high-level trigger and data acquisition system, the pixel data reduction using regions of interest was exercised. We investigated the data produced in more than 20 million events and verified that the ONSEN system behaved correctly, forwarding all pixels inside regions of interest and discarding the rest.

Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board

With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.

The data acquisition system of the Belle II Pixel Detector

At the future Belle II experiment the DEPFET (DEPleted Field EffectTransistor) pixel detector will consist of about 8 million channelsand is placed as the innermost detector. Because of its small distanceto the interaction region and the high luminosity in Belle II, for atrigger rate of about 30 kHz with an estimated occupancyof about 3 % a data rate of about 22 GB/s isexpected. Due to the high data rate, a data reduction factor higherthan 30 is needed in order to stay inside the specifications of theevent builder.The main hardware to reduce the data rate is a xTCA based Compute Node(CN) developed in cooperation between IHEP Beijing and UniversityGiessen. Each node has as main component a Xilinx Virtex-5 FX70T FPGAand is equipped with 2 × 2 GB RAM , GBit Ethernet and4 × 6.25 Gb/s optical links. An ATCA carrier board isable to hold up to four CN and supplies high bandwidth connectionsbetween the four CNs and to the ATCA backplane.To achieve the required data reduction on the CNs, regions of interest(ROI) are used. These regions are calculated in two independentsystems by projecting tracks back to the pixel detector. One is theHigh Level Trigger (HLT) which uses data from the Silicon VertexDetector (SVD), a silicon strip detector, and outer detectors. Theother is the Data Concentrator (DATCON) which calculates ROIs based onSVD data only, in order to get low momentum tracks. With thisinformation, only PXD data inside these ROIs will be forwarded to theevent builder, while data outside of these regions will be discarded.First results of the test beam time in January 2014 at DESY with aBelle II vertex detector prototype and full DAQ chain will bepresented.

Linear mode photon counting with the noiseless gain HgCdTe e-avalanche photodiode

A linear mode photon counting focal plane array using HgCdTe mid-wave infrared (MWIR) cutoff electron initiated avalanche photodiodes (e-APDs) has been designed, fabricated, and characterized. The broad spectral range (0.4 to 4.3 μm) is unique among photon counters, making this a “first of its kind” system spanning the visible to the MWIR. The low excess noise [F(M)≈1] of the e-APDs allows for robust photon detection while operating at a stable linear avalanche gain in the range of 500–1000. The readout integrated circuit (ROIC) design included a very high gain-bandwidth product resistive transimpedance amplifier (3×1013 Ω-Hz) and a 4 ns output digital pulse width comparator. The ROIC had 16 high-bandwidth analogs and 16 low-voltage differential signaling digital outputs. The 2×8 array was integrated into an LN2 Dewar with a custom leadless chip carrier and daughter board design that preserved high-bandwidth analog and digital signal integrity. The 2×8 e-APD arrays were fabricated on 4.3 μm cutoff HgCdTe and operated at 84 K. The measured dark currents were approximately 1 pA at 13 V bias where the measured avalanche photodiode gain was 500. This translates to a predicted dark current induced dark count rate of less than 20 KHz. Single photon detection was achieved with a photon pulse signal-to-noise ratio of 13.7 above the amplifier noise floor. A photon detection efficiency of 50% was measured at a photon background limited false event rate of about 1 MHz. The measured jitter was in the range of 550–800 ps. The demonstrated minimum time between distinguishable events was less than 10 ns.

The Belle II Pixel Detector Data Acquisition and Reduction System

The upcoming Belle II experiment is designed to work at a luminosity of 8×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">35</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , 40 times higher than its predecessor. The pixel detector of Belle II with its ~ 8 million channels will deliver ten times more data than all other sub-detectors together. A data rate of 22 Gbytes/s is expected for a trigger rate of 30 kHz and an estimated pixel detector occupancy of 3%, which is by far exceeding the specifications of the Belle II event builder system. Therefore a realtime data reduction of a factor > 30 is needed. A hardware platform capable of processing this amount of data is the ATCA based Compute Node (CN). Each CN consists of an xTCA carrier board and four AMC/xTCA daughter boards. The carrier board supplies the high bandwidth connectivity to the other CNs via Rocket-IO links. In the current prototype design, each AMC board is equipped with a Xilinx Virtex-5 FX70T FPGA, 4 GB of memory, Gbit Ethernet and two bi-directional optical links allowing for a bandwidth of up to 12.5 Gbits/s. IPMI control of mother and daughter board is foreseen. One ATCA shelf containing 10 mother boards/40 daughter boards is sufficient to process the data from the 40 front end boards. The data reduction on the CN is done in two steps. First, the event data delivered by the front end electronics via optical links is stored in memory until the high level trigger (HLT) decision has been made. The HLT rejects >2/3 of these events. In a second step, pixel data of positively triggered events is reduced with the help of regions of interest (ROI), calculated by the HLT from projecting trajectories back to the pixel detector plane. The design allows additional ROI inputs computed from hit cluster properties or tracklets from the surrounding silicon strip detector. The final data reduction is achieved by sending only data within these ROIs to the main event builder.

Grid Assembly-Free 60-GHz Antenna Module Embedded in FR-4 Transceiver Carrier Board

A novel antenna module solution which dramatically alleviates cost and fabrication related limitations of traditional 60-GHz antenna modules is demonstrated. The antenna topology is wholly devised using industry standard FR-4 PCB and is integrated into the 60-GHz transceiver carrier board. As a result, the proposed approach effectively bypasses the need for any complicated grid array assemblies for the first time to the author's best knowledge. The antenna element is first designed and confirmed to exhibit more than 9-GHz bandwidth and 71% average radiation efficiency from 57–66 GHz. The design is further expanded into an 8-element phased array module and integrated with a 60-GHz RFIC transceiver and digital interface. The overall footprint of the antenna module within the carrier board is 20 $\,\times\,$ 20 $\,\times\,$ 0.838 mm $^{3}$ . System-level evaluation confirms the 8-element phased array module to be highly sufficient in scan range, side lobe levels and radiation efficiency for 60-GHz wireless systems, particularly in the field of consumer electronics.

The LAMBDA photon-counting pixel detector

The Medipix3 photon-counting detector chip has a number of novel features that are attractive for synchrotron experiments, such as a high frame rate with zero dead time and high spatial resolution. DESY are developing a large-area Medipix3-based detector array (LAMBDA). A single LAMBDA module consists of 2 by 6 Medipix3 chips on a ceramic carrier board, bonded to either a single large silicon sensor or two smaller high-Z sensors. The readout system fits behind the carrier board to allow module tiling, and uses a large on-board RAM and multiple 10 Gigabit Ethernet links to permit high-speed readout. Currently, the first large silicon modules have been constructed and read out at low speed, and the firmware for highspeed readout is being developed. In addition to these silicon sensors, we are developing a germanium hybrid pixel detector in collaboration with Canberra for higher-energy beamlines. Canberra have produced a set of 256-by-256-pixel planar germanium sensors with 55μm pitch, and these are currently being bonded to Medipix3 readout chips by Fraunhofer IZM (Berlin).

Recent developments for the upgrade of the LHCb readout system

The upgraded LHCb readout system aims at a trigger-free readout of the entire detector at the bunch-crossing rate. This implies a major architectural change for the readout system that must capture the data at 40 MHz instead of 1 MHz. One of the key components of this upgrade system is the readout board.The LHCb collaboration has chosen to evaluate the ATCA architecture as form-factor for the readout board. The readout system architecture relies on a unique board able to satisfy all the requirements for data transmission, timing and fast control as well as experiment control system. A generic ATCA carrier board has been developped. It is equipped with four dense AMC mezzanines able to interface a total of 144 bidirectional optical links at up to 10 Gbits/s. This board embeds 4 high end Stratix V GX devices for data processing and a programmable set of commutation functions allowing to reconfigure the connectivity of the system in a flexible way.The overall architecture will be presented and how the cards map over each functionality.First results and measurements will be described in particular those related to the use of new highly integrated optical devices.At last we will present the incremental development methodology used in this project.

LAMBDA — Large Area Medipix3-Based Detector Array

Medipix3 is a photon-counting readout chip for X-ray detection. It has a small pixel size (55 μm) and a high frame rate with zero dead time, which makes it attractive for experiments at synchrotrons. Using Medipix3, DESY are developing the LAMBDA (Large Area Medipix3-Based Detector Array) system. A single LAMBDA module carries either a single large silicon sensor of 1536 by 512 pixels, or two smaller high-Z sensors. The sensor is bonded to 12 Medipix3 chips, and mounted on a ceramic carrier board. The readout system for the module then provides a fast FPGA, a large RAM and four 10 Gigabit Ethernet links to allow operation at high frame rates. Multiple modules may then be tiled together a larger area. Currently, the first large silicon modules have been constructed and tested at low speed, and the firmware for fast readout is being developed.