Carbon Nanotube Field-effect Transistors Research Articles

Recent Fundamental Advances in Quality of High-Performance and Highly-Scaled Carbon Nanotube Transistors

Recently a number of breakthroughs have been reported by our team in the component qualities of transistors built on Carbon Nanotube (CNT) channels. However, any emerging channel material which seeks to outperform established semiconductors for transistor logic applications has a substantial hill to climb, given the incredible capabilities of advanced Si-based logic technology platforms. This talk will first aim to frame our progress on Carbon Nanotube CMOS technology in the broader context of the value proposition and desired component qualities needed to realize practical impact in computing applications. Next, we will share advances in the fundamental building blocks for Carbon Nanotube transistors towards these targets including channel, contact, doping, and gate-stack modules. Finally we will describe new record CNT MOSFET performance milestones achieved by integrating best available device components for first time, which gives insight into the remaining performance limiters and future directions.[1] G. Pitner, et al., "Building High Performance Transistors on Carbon Nanotube Channel," VLSI 2023.[2] S. Li, et al., "High-Performance and Low Parasitic Capacitance CNT MOSFET: 1.2 mA/um at Vds of 0.75 V by self-aligned doping in sub-20 nm spacer," IEDM 2023.[3] N. Safron, et al., "Low N-type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping," IEDM 2023.[4] H.-Y. Chiu, et al., "Self-Aligned Contact Doping for Performance Enhancement of Low-Leakage Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023.[5] T.A. Chao, et al., "Small Molecule Additives to Suppress Bundling in Dimensional-Liminted Self-Alignment Method for High-Density Aligned CNT Array," Advanced Materials Interfaces, 2023.[6] Q. Lin, et al., " Band-to-Band Tunneling Leakage Current Characterization and Projection in Carbon Nanotube Transistors," ACS Nano 2023.[7] Z. Zhang, et al., "Complementary Carbon Nanotube Metal-Oxide-Semicondcutor Field-Effect Transistors with Localized Solid-State Extension DOping," Nature Electronics, 2023.[8] S.K. Su, et al., " Perspective on Low-Dimensional Channel Materials for Extremely Scaled CMOS," VLSI 2022.[9] Z. Zhang, et al., "Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth," ACS Applied aterials & Interfaces, 2022.[10] G. Pitner, et al., "Sub-0.5 nm Interfacial Dielectrics Enables Superior Electrostatics: 65 mV/dec top-gated Carbon Nanotube FETs at 15 nm gate length," IEDM 2020.

Nonideality in Arrayed Carbon Nanotube Field Effect Transistors Revealed by High-Resolution Transmission Electron Microscopy.

High density and high semiconducting-purity single-walled carbon nanotube array (A-CNT) have recently been demonstrated as promising candidates for high-performance nanoelectronics. Knowledge of the structures and arrangement of CNTs within the arrays and their interfaces to neighboring CNTs, metal contacts, and dielectrics, as the key components of an A-CNT field effect transistor (FET), is essential for device mechanistic understanding and further optimization, particularly considering that the current technologies for the fabrication of A-CNT wafers are mainly laboratory-level solution-based processes. Here, we conduct a systematic investigation into the microstructures of A-CNT FETs mainly via cross-sectional high-resolution transmission electron microscopy and tentatively establish a framework consisting of up to 11 parameters which can be used for structure-side quality evaluation of the A-CNT FETs. The parameter ensemble includes the diameter, length (or terminal), and density distribution of CNTs, radial deformation of CNTs, array alignment defects, surface crystallography facets of contact metal, thickness distribution of high-k dielectrics (HfO2), and the contact ratios for the CNT-CNT, CNT-metal, CNT-dielectric, and CNT-substrate interfaces. Enriched array alignment defects, i.e., bundle, stacking, misorientation, and voids, are observed with a total ratio sometimes up to ∼90% in pristine A-CNTs and even up to ∼95% after the device fabrication process. Thus, they are suggested as the prevalent performance-limiting factors for A-CNT FETs. Complex interfacial structures are observed at the CNT-CNT, CNT-metal contact, and CNT-high-k dielectric interfaces, making the local environment and the property of each component CNT involved in an A-CNT FET distinct from others in terms of the diameters, radial deformation, and interactions with the local surroundings (mainly through van der Waals interactions). The present study suggests further improvements on the fabrication technology of A-CNT wafers and devices and mechanistic investigations into the impacts of complex array alignment defects and interface structures on the electrical performance of A-CNT FETs as well.

DM-PA-CNTFET Biosensor for Breast Cancer Detection: Analytical Model

In this paper, an analytical model for a novel design dielectric modulated plasma-assisted carbon nanotube field-effect transistor (DM-PA-CNTFET) biosensor is proposed for breast cancer detection. This work is based on a PA-CNTFET in which CNT is used as a channel of FET, and various other device engineering techniques such as dual metal gate-all-around structure and dielectric stack of SiO2 and HfO2 have been used. A comparative analysis of DS-GAAE-CNTFET was performed using a silicon gate all-around FET (Silicon-GAA-FET)-based biosensor. Early detection of breast cancer is made possible by immobilizing MDA-MB-231 and HS578t into the dual-sided nanocavity, which alters the electrical properties of the proposed CNTFET-based biosensor. The DS-GAAE-CNTFET sensor demonstrates a drain ON current sensitivity of 236.9 nA and a threshold voltage sensitivity of 285.58 mV for HS578t cancer cells. Malignant MDA-MB-231 breast cells exhibit a higher drain ON current sensitivity of 343.35 nA and a corresponding threshold voltage sensitivity of 293.23 mV. The exceptional sensitivity and structural resilience of the DS-GAAE-CNTFET biosensor establish it as a promising candidate for early breast cancer detection.

CNTFET-Based Single-Ended Fractional Order Colpitts Oscillator: Design, Simulation and Comparative Analysis

In this paper, we design and simulate a Single-Ended Colpitts Oscillator (CO) in integer and fractional order domains. The oscillators are realized in 32[Formula: see text]nm node conventional MOSFET and carbon nanotube field effect transistor (CNTFET) technologies. Therefore, four COs have been designed, simulated and rigorously compared. These include integer order conventional MOSFET-based CO, fractional order MOSFET-based CO, CNTFET-based integer order CO and CNTFET-based fractional order CO, all based on 32-nm technology nodes. The fractional order approach has been used as it results in better control over the phase and frequency of the oscillator. Herein, fractional order capacitors of various orders, used in realizing the fractional order COs, are realized and their frequency responses are studied. This is being done to ensure whether the designed pseudo-capacitances have fractional behavior or not in the desired frequency and phase spectrum. It has been observed that the variation of fractional order [Formula: see text] from 0.4 to 0.81 has resulted in a slight reduction of oscillation frequency from 1.68[Formula: see text]GHz ([Formula: see text]) to 1.351[Formula: see text]GHz ([Formula: see text]) keeping the pseudo-capacitance same at 0.3[Formula: see text]nF in MOS-based topology. Since the fractional order realization increases the circuit complexity and power consumption, therefore, CNTFET-based integer order as well as fractional order COs have been designed. The CNTFET-based fractional order CO retains the advantages of the fractional order domain as well as the power efficiency of CNTFETs. Further, it has been observed that integrating fractional-order capacitor (FOC) with the CNTFET CO results in a much larger constant phase zone (CPZ), an important performance measuring parameter. A rigorous comparative analysis of the four COs designed in this work has been performed.

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

Enzymatic cascade reactors on carbon nanotube transistor detecting trace prostate cancer biomarker

Biosensors based on carbon nanotube field-effect transistors (CNT-FETs) have shown great potential in biomarker detection due to their high sensitivity because of appreciable semiconducting electrical properties. However, background signal interferences in complex mediums may results in low signal-to-noise ratio, which may impose challenges for precise biomarker detection in physiological fluids. In this work, we develop an enzymatic CNT-FET, with scalable production at wafer scale, for detection of trace sarcosine that is a biopsy-correlated biomarker of prostate cancer. Enzymatic cascade rectors are constructed on the CNT to improve the reaction efficiency, thereby, enhancing the signal transduction. As such, a limit of detection as low as 105 zM is achieved in buffer solution. Owing to the enhanced reaction efficiency, the testing of clinical serum samples yields significant signal difference to discriminate the prostate cancer (PCa) samples from the benign prostatic hyperplasia (BPH) samples (P = 1.07 × 10−5), demonstrating immense potential in practical applications.

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Multi-valued logic (MVL) extends binary logic by providing a framework to represent complex systems with more than two truth values. MVL was introduced to confront the enormous interconnect issue associated with the binary logic in implementing the presnt day complex nanoelectronic architectures. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFETs), combined with the ability of resistive random-access memory (RRAM) to store multiple resistance values, has enabled the design of quaternary logic gates and arithmetic circuits. A new CNTFET-based design architecture has been proposed to implement the quaternary logic compatible with the existing technologies. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration. The static power reduction due to the effecciency of the design architecture and high OFF state resistance offered by integrating RRAM into the logic design was explored.The proposed circuits have been subject to various types of parameter variations to validate thir proper functionality in presence of these variations.

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM cell was simulated using the HSPICE tool with a VDD of 0.9 V. The high-speed and low-power characteristics of the SRAM design are attributed to the high subthreshold slope and high carrier mobility of metal-oxide-semiconductor field-effect transistor (MOSFET)-like CNTFETs utilized in the simulations. The implementation of dual threshold transistors, coupled with a transmission gate for bitline access, contributes to the enhanced performance. Key performance metrics such as noise margins, power consumption, delay, and SRAM electrical quality metric (SEQM) of the proposed SRAM have been evaluated and compared with existing CNTFET-based SRAM designs. The proposed cell demonstrates reductions of 73.73%, 43.18%, and 58.70% in read power, write power, and hold power, respectively, compared to the lowest respective power values of other examined SRAM designs. The proposed SRAM ranks second, third, and second in write static noise margin (WSNM), hold static noise margin (HSNM), and read static noise margin (RSNM), respectively, among other designs. Additionally, the proposed SRAM exhibits the least sensitivity to parametric variations compared to other designs. The SEQM, which provides a comprehensive assessment of access times, noise margins, and power usage for the SRAM cell, has been calculated. The SEQM of the proposed SRAM is 10.6, 1.89, 13.15, and 1.82 times higher than that of C6T, BLP8T, Mani’s 10 T, and LP8T, respectively.

Duffy Antigen Receptor for Chemokines (DARC) Nanodisc-Based Biosensor for Detection of Staphylococcal Bicomponent Pore-Forming Leukocidins.

Staphylococcus aureus (S. aureus) is an opportunistic infectious pathogen, which causes a high mortality rate during bloodstream infections. The early detection of virulent strains in patients' blood samples is of medical interest for rapid diagnosis. The main virulent factors identified in patient isolates include leukocidins that bind to specific membrane receptors and lyse immune cells and erythrocytes. Duffy antigen receptor for chemokines (DARC) on the surface of specific cells is a main target of leukocidins such as gamma-hemolysin AB (HlgAB) and leukocidin ED (LukED). Among them, HlgAB is a conserved and critical leukocidin that binds to DARC and forms pores on the cell membranes, leading to cell lysis. Current methods are based on ELISA or bacterial culture, which takes hours to days. For detecting HlgAB with faster response and higher sensitivity, we developed a biosensor that combines single-walled carbon nanotube field effect transistors (swCNT-FETs) with immobilized DARC receptors as biosensing elements. DARC was purified from a bacterial expression system and successfully reconstituted into nanodiscs that preserve binding capability for HlgAB. Dynamic light scattering (DLS) and scanning electron microscopy (SEM) showed an increase of the DARC-containing nanodisc size in the presence of HlgAB, indicating the formation of HlgAB prepore or pore complexes. We demonstrate that this sensor can specifically detect the leukocidins HlgA and HlgAB in a quantitative manner within the dynamic range of 1 fM to 100 pM with an LOD of 0.122 fM and an LOQ of 0.441 fM. The sensor was challenged with human serum spiked with HlgAB as simulated clinical samples. After dilution for decreasing nonspecific binding, it selectively detected the toxin with a similar detection range and apparent dissociation constant as in the buffer. This biosensor was demonstrated with remarkable sensitivity to detect HlgAB rapidly and has the potential as a tool for fundamental research and clinical applications, although this sensor cannot differentiate between HlgAB and LukED as both have the same receptor.

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

Band alignment and charge transfer mechanisms in the prediction of advanced gate dielectrics for carbon nanotube field-effect transistors

The search for novel gate dielectrics to mitigate interface state density is a pressing concern in the fabrication of high-performance carbon nanotube field-effect transistors (CNT-FETs). In this study, we investigated the feasibility of employing strontium titanate (STO) with an ultra-high dielectric constant as the gate dielectric in CNT-FETs. By combining X-ray photoelectron spectroscopy measurements with first-principles calculations, we determined the band offsets between CNT and STO, as well as between CNT and conventional gate dielectrics such as HfO2 and SiO2. The valence/conduction band offset (VBO/CBO) at the STO/CNT interface is found to be 1.1 eV/1.5 eV, which is the smallest among all studied interfaces, followed by those at HfO2/CNT interface (VBO = 1.3 eV/CBO = 3.4 eV) and SiO2/CNT interface (VBO = 3.6 eV/CBO = 4.5 eV). Moreover, charge transfer at the STO/CNT interface exhibits two orders of magnitude lower values compared to that at HfO2/CNT interface and is also significantly smaller than that at SiO2/CNT interface. This phenomenon can be ascribed to the combined effects of van der Waals forces at the STO/CNT interface and fewer dangling bonds on the STO surface. These findings suggest exceptional compatibility between STO and CNT, making STO highly suitable for high-performance CNT-FETs.

Label-Free and Ultrasensitive Detection of Cartilage Acidic Protein 1 in Osteoarthritis Using a Single-Walled Carbon Nanotube Field-Effect Transistor Biosensor.

Osteoarthritis (OA), a prevalent degenerative joint disease, significantly affects the well-being of afflicted individuals and compromises the standard functionality of human joints. The emerging biomarker, Cartilage acidic protein 1 (CRTAC1), intricately associates with OA initiation and serves as a prognostic indicator for the trajectory toward joint replacement. However, existing diagnostic methods for CRTAC1 are hampered by the limited abundance, thus restricting the precision and specificity. Herein, a novel approach utilizing a single-walled carbon nanotube field-effect transistor (SWCNTs FET) biosensor is reported for the direct label-free detection of CRTAC1. High-purity semiconducting carbon nanotube films, functionalized with antibodies of CRTAC1, provide excellent electrical and sensing properties. The SWCNTs FET biosensor exhibits high sensitivity, notable reproducibility, and a wide linear detection range (1 fg/mL to 100 ng/mL) for CRTAC1 with a theoretical limit of detection (LOD) of 0.2 fg/mL. Moreover, the SWCNTs FET biosensor is capable of directly detecting human serum samples, showing excellent sensing performance in differentiating clinical samples from OA patients and healthy populations. Comparative analysis with traditional enzyme-linked immunosorbent assay (ELISA) reveals that the proposed biosensor demonstrates faster detection speeds, higher sensitivity/accuracy, and lower errors, indicating high potential for the early OA diagnosis. Furthermore, the SWCNTs FET biosensor has good scalability for the combined diagnosis and measurement of multiple disease markers, thereby significantly expanding the application of SWCNTs FETs in biosensing and clinical diagnostics.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Design and performance evaluation of a novel parallel kinematic micromanipulator

The targeted placement of selected carbon nanotubes is associated with low throughput rates. Hence, this paper presents a novel stage design for the fully automatic assembly of carbon nanotube field-effect transistors (CNTFETs) via mechanical dry transfer. It constitutes the core module of an assembly machine for the precise deployment of nanotubes onto a prefabricated wafer. The mechanical dry transfer approach allows high level of carbon nanotube selectivity with the aim of enabling a high-volume fabrication of ultra-clean devices. The previous production rate of such ultra-clean devices is less than one per hour, which offers a high potential for improvement. The stage consists of a parallel kinematic mechanism (PKM) with 3 degrees of freedom (X2Y2C1) carrying two additional stacked axes (Z1C2). The PKM is suspended on a vacuum preloaded aerostatic bearing, voice coil motors (VCM) and flexure hinges. Together with a combination of high precision and resolution touch probe measurement systems close to its tool center point (TCP), high accuracy and low settling time can be achieved. Based on realistic manufacturing tolerances, a sensitivity analysis of the mechanism’s pseudo rigid body model (PRBM) suggests a theoretical closed-loop error below 0.15μm over the entire XY workspace of 20mm×2.8mm. Measurements of positioning motions show that the settling time can be decreased by the compensation of friction resistances inside the internal bearings of the VCMs.

Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution.

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore's era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

Spintronic device in SWCNT-FET configuration based on chromium oxides thin films consisting of half-metallic ferromagnetic CrO2

Spintronic device architectures consisting of ferromagnetic chromium oxide electrodes in single-walled carbon nanotubes field effect transistor (SWCNT-FET) configuration have been fabricated to act as strategic building blocks for next generation super-compact high-speed nanoelectronic devices for logic and memory operations. Stable thin films of chromium oxides consisting of half-metallic ferromagnetic chromium-di-oxide (CrO2) were pulsed laser deposited (PLD) over lattice-matched rutile-type-tetragonal intermediate TiO2 thin layers over thermally oxidized Si substrates for engineering of the spintronic device structure. Focused ion beam (FIB) milling was applied to the ferromagnetic chromium oxide thin films for patterning of the source (S) and (D) electrodes. Typical electrical characteristics derived by lnρ vs. T−1/2 plots confirmed spin-dependent transport (SDT) as the dominant mechanism of electrical conduction upto temperatures of ∼280 K along with negative magnetoresistance (MR) of ∼30 % at 278 K. Electrical characteristics (output and transfer) of the spintronic device structure were drawn under application of magnetic field (H) in out-of-plane geometry at the temperatures of 5.6 K, 250 K & 300 K. Drain current (Id) is demonstrated to be controlled effectively as a function of gate bias (Vg) for different fixed Vd-biases at all the device operating temperatures. Change in %MR as a function of gate voltage (Vg) was acquired at T = 250 &T = 300 K that displayed higher %MR change under out-of-plane geometry of applied field of 0.75 T of the spintronic device operation.

Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors

Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

Optimized Design of Carbon Nanotube Field-Effect Transistor Using Taguchi Method for Enhanced Current Ratio Performance

Abstract Presently, the integrated circuit (IC) industry grapples with obstacles in downsizing MOSFET technology further, hindered by its inherent physical constraints. Therefore, the substitution of silicon with carbon nanotubes (CNTs) holds promise for paving a novel path in semiconductor industries, driven by their diminutive dimensions and superior electrical properties. Hence, this project employed SILVACO ATLAS software in conjunction with the Taguchi method to refine a CNTFET design for optimal performance. In this work, response variables consists of on-current (Ion), current ratio (Ion/Ioff) and threshold voltage (Vth) are extracted. In this particular design, the Taguchi method was employed to ascertain the most effective combination of design parameters and materials to achieve optimal CNTFET performance, as assessed by the three key response variables. The design parameter and material that had been chosen were the diameter of carbon nanotube (Dcnt), dielectric material (K) and oxide thickness (tox). Each of the design parameters and material had three different values. For K, the values are 3.9 (SiO2), 25 (ZrO2) and 80 (TiO2). While for Dcnt and tox, the values are 4.0 nm, 6.0 nm, 8.0 nm and 2.0 nm, 4.0 nm, 6.0 nm respectively. According to the Taguchi optimization findings, the ideal combination of parameters comprises a CNT diameter of 4.0 nm, an oxide thickness of 2.0 nm, and the use of TiO2 (80) as the dielectric material. The ANOVA analysis underscores the significance of prioritizing optimization efforts towards the CNT diameter parameter. This is attributed to its substantial contribution, accounting for 93.55% of the variation in the Ion/Ioff value, surpassing the influence of dielectric materials and oxide thickness.

Design and Analysis of Digitally Tunable Transconductance Amplifier (DTTA) Using CNTFETs.

Carbon nanotube-FETs (CNTFETs) have become a potential challenger because of their exceptional electrical properties and compatibility with conventional CMOS technology. The design and study of digitally tunable transconductance amplifiers (DTTAs) using CNTFETs are the main topics of this work. By utilizing the special characteristics of CNTFETs, the suggested DTTA design makes transconductance tunable, providing a versatile method of adjusting amplifier settings without requiring modifications to the hardware architecture. This study provides a complete description of the CNTFET modeling techniques utilized for realistic circuit simulations, along with a detailed analysis of the DTTA based on CNTFETs. The circuit is implemented using a 32 nm CNTFET model and verified results with HSPICE.