Carbon Nanotube Thin-film Transistors Research Articles

Lowering interface state density in carbon nanotube thin film transistors through using stacked Y2O3/HfO2 gate dielectric

Wafer-scale fabrication of transistors is the prerequisite for practical applications of carbon nanotube (CNT) based electronics. In this work, we fabricated top-gated thin film transistors (TFTs) based on solution-derived CNT film prepared on a 2 in. substrate through a photolithography based process. In particular, we improved the gate dielectric layer in CNT TFTs through using a thin thermal oxidized Y2O3 film as a buffer layer before the growth of high-κHfO2 layer. The introduction of the Y2O3 film significantly enhanced the performance of CNT TFTs, including the improved on-state current and transconductance, lowered threshold voltage and subthreshold swing, and drastically enhanced carrier mobility, owing to the reduction of the interface state density and scattering centers. Quantitative extraction of the interface state density based on either capacitance-voltage measurements or subthreshold swing data further demonstrates that the introduction of the Y2O3 interlayer reduces the interface state density from 9.24 × 1012 cm−2 to 4.63 × 1012 cm−2 in the gate insulator.

Biosensor response from target molecules with inhomogeneous charge localization

We analyzed the sensor response from aptamer-modified carbon nanotube thin film transistors that adsorb immunoglobulin E (IgE) with an inhomogeneous charge distribution. The net charge of the target molecules within the Debye length reflects the polarity of the electrical sensor signal. The complicated sensor response, which depends on the Debye length, can be interpreted by two kinds of adsorption states considering the influence of steric hindrance by previously adsorbed IgE molecules. These results explain the anomalous behavior of the sensor response in previous reports and pave the way to control the dynamic range.

(Invited) Carbon Nanotube Transistors for Flat Panel Display Application

Carbon nanotubes are promising materials which can provide more functions at low cost for macroelectronics application, such as backplane electronics for display, flexible electronics, bio-chemical sensors, solar cells and others. Among these macroelectronics applications, carbon nanotube thin film transistors (CNT-TFTs) are expected to be used soon for backplanes electronics in flat panel displays (FPDs). This is due to the performance of CNT-TFTs surpasses the current commercialized TFT technologies, e.g., high mobility, high on/off ratio and high on-current surpass. Moreover, the fabrication process of CNT-TFTs is regarded facile, scalable, and compatible with the current TFT manufacturing process. Prototype AMOLED devices driven by CNT-TFTs have been demonstrated. However, most of the efforts on the application of CNT-TFTs for the backplane electronics are in research laboratories, and there are still many challenges before it is commercialized. In this presentation, we will report our progress on CNT-TFTs for FPD application, which includes the following aspects: high efficient fabrication of highly uniform carbon nanotube films on large area substrates (from 4 inch silicon wafers to 2.5th generation backplane glasses (370mm × 470mm)), manufacturing compatible fabrication process of CNT-TFTs, contact effect on the performance and scaling behavior of CNT-TFTs, hysteresis and ambipolarity suppression. Our results indicate practical application of CNT-TFTs in FPD products is expectable in a near future.

On/Off Ratio Improvement of Carbon Nanotube Thin Film Transistors By Combining Asymmetric Gate Design and Chemical Doping

Carbon nanotubes are regarded promising building blocks for the future nanoelectronics. High performance transistors and integrated circuits based on semiconducting CNT thin films, e.g., CMOS type 4-bit adder, CNT computer, flexible sensor etc., have been reported. These progresses demonstrate the CNT transistor technology is being pushed to practical application. For real circuits applications, high Ion/Ioff ratio with low Ioff for a transistor are required in high speed and low power consumption integrated circuits. However, the switching behavior of most reported CNT thin film transistors are not good enough. Due to the intrinsic ambipolarity of CNTs, the Ioff values are usually higher than hundreds of nano Ampe and the Ion/Ioff ratio is decreased to less than 102 at relatively high source/drain bias voltages (e.g. 1V). Though the switching behavior of the FETs based on individual CNTs can be improved by either special design of the device geometry or chemical doping, these methods do not work well in CNT thin film transistors. In this work, we improved the performance of CNT thin film transistors by combining the asymmetric gate design and chemical doping. In this way, the Ioff was suppressed while the Ion was increased at the mean time. Thus the Ion/Ioff ratio was increased by ~2 orders of magnitude when compared with normally designed top-gate device. Moreover, the devices showed better subthreshold swing (SS) and the threshold voltage (Vth) was closer to zero than normal devices. These improvements are benefit to more complicated circuits design, and our method is applicable for the emerging nanodevices.

Capacitively Coupled Hybrid Ion Gel and Carbon Nanotube Thin‐Film Transistors for Low Voltage Flexible Logic Circuits

AbstractThe lamination of a high‐capacitance ion gel dielectric layer onto semiconducting carbon nanotube (CNT) thin‐film transistors (TFTs) that are bottom‐gated with a low‐capacitance polymer dielectric layer drastically reduces the operating voltage of the devices resulting from the capacitive coupling effect between the two dielectric layers sandwiching the CNT channel. As the CNT channel has a network structure, only a compact area of ion gel is required to make the capacitive coupling effect viable, unlike the planar channels of previously reported transistors that required a substantially larger area of ion gel dielectric layer to induce the coupling effect. The capacitively coupled CNT TFTs possess superlative electrical characteristics such as high carrier mobilities (42.0 cm2 (Vs)−1 for holes and 59.1 cm2 (Vs)−1 for electrons), steep subthreshold swings (160 mV dec−1 for holes and 100 mV dec−1 for electrons), and low gate leakage currents (<1 nA). These devices can be further integrated to form complex logic circuits on flexible substrates with high mechanical resilience. The layered geometry of the device coupled with scalable solution‐based fabrication has significant potential for large‐scale flexible electronics.

Ultraviolet/ozone and oxygen plasma treatments for improving the contact of carbon nanotube thin film transistors

Carbon nanotube thin film transistor (CNT-TFT) is an emerging technology for future macroelectronics, such as chemical and biological sensors, optical detectors, and the backplane driving circuits for flat panel displays. The mostly reported fabrication method of CNT-TFT is a lift-off based photolithography process. In such fabrication process, photoresist (PR) residue contaminates the interface of tube-metal contact and deteriorates the device performance. In this paper, ultraviolet ozone (UVO) and oxygen plasma treatments were employed to remove the PR contamination. Through our well-designed experiments, the UVO treatment is confirmed an effective way of cleaning contamination at the tube-metal interface, while oxygen plasma treatment is too reactive and hard to control, which is not appropriate for CNT-TFTs. It is determined that 2–6 min UVO treatment is the preferred window, and the best optimized treatment time is 4 min, which leads to 15% enhancement of device performance.

Hybrid complementary inverter based on carbon nanotube and IGZO thin-film transistors with controlled process conditions

Carbon nanotubes (CNTs) and indium-gallium-zinc oxide (IGZO) have emerged as important materials for p-type and n-type thin-film transistors (TFTs), respectively, due to their high mobility, flexibility, and low fabrication temperature. However, fabricating sophisticated macroelectronic circuits operating in complementary mode is challenging using only a single material, because implementing n-type CNT TFTs and p-type IGZO TFTs is difficult. Therefore, hybrid complementary circuits integrated with p-type CNT TFTs and n-type IGZO TFTs have been demonstrated to combine the strength of each TFT. However, limited efforts have been devoted to optimizing the circuit performance by tuning the process conditions under which the percolated CNT network channel and IGZO channel are formed. In particular, the densities of CNTs in the network channel and the amount of oxygen vacancies in the IGZO channel can be simply adjusted, which are important in determining the electrical properties of each TFT. In this work, we systematically investigated the device and circuit performance by varying such conditions; hence, we confirmed the design features of each TFT that can be optimized to enhance the hybrid complementary circuits.

Voltage-Controlled Spray Deposition of Multiwalled Carbon Nanotubes on Semiconducting and Insulating Substrates

A facile, cost-effective, voltage-controlled, “single-step” method for spray deposition of surfactant-assisted dispersed carbon nanotube (CNT) thin films on semiconducting and insulating substrates has been developed. The fabrication strategy enables direct deposition and adhesion of CNT films on target samples, eliminating the need for substrate surface functionalization with organosilane binder agents or metal layer coatings. Spray coating experiments on four types of sample [bare silicon (Si), microscopy-grade glass samples, silicon dioxide (SiO2), and polymethyl methacrylate (PMMA)] under optimized control parameters produced films with thickness ranging from 40 nm to 6 μm with substantial surface coverage and packing density. These unique deposition results on both semiconducting and insulator target samples suggest potential applications of this technique in CNT thin-film transistors with different gate dielectrics, bendable electronics, and novel CNT-based sensing devices, and bodes well for further investigation into thin-film coatings of various inorganic, organic, and hybrid nanomaterials on different types of substrate.

All-Printed, Self-Aligned Carbon Nanotube Thin-Film Transistors on Imprinted Plastic Substrates.

We present a self-aligned process for printing thin-film transistors (TFTs) on plastic with single-walled carbon nanotube (SWCNT) networks as the channel material. The SCALE (self-aligned capillarity-assisted lithography for electronics) process combines imprint lithography with inkjet printing. Specifically, inks are jetted into imprinted reservoirs, where they then flow into narrow device cavities due to capillarity. Here, we incorporate a composite high- k gate dielectric and an aligned conducting polymer gate electrode in the SCALE process to enable a smaller areal footprint than prior designs that yields low-voltage SWCNT TFTs with average p-type carrier mobilities of 4 cm2/V·s and ON/OFF current ratios of 104. Our work demonstrates the promising potential of the SCALE process to fabricate SWCNT-based TFTs with favorable I- V characteristics on plastic substrates.

In-Place Printing of Carbon Nanotube Transistors at Low Temperature

Interest in flexible, stretchable, and wearable electronics has motivated the development of additive printing to fabricate customizable devices and systems directly onto virtually any surface. However, progress has been limited by the relatively high temperatures (>200 °C) required to sinter metallic inks and time-consuming process steps, many of which require removal of the substrate from the printer for coating, washing, or sintering. In this work, we addressed these challenges and demonstrate carbon nanotube thin-film transistors (CNT-TFTs) that are fabricated by aerosol jet printing with the substrate never leaving the printer. The full in-place printing approach, from first step to last, used a maximum process temperature of only 80 °C on the printer platen. Silver nanowire (Ag NW) ink was found to be most viable for low-temperature, in-place sintering while still yielding good electrical interfaces to the CNT thin-film channels. These aerosol-jet printed Ag NW films were conductive immediately afte...

Large-area and highly uniform carbon nanotube film for high-performance thin film transistors

Carbon nanotube thin film transistors (CNT-TFTs) are a potential TFT technology for future high-performance macroelectronics. Practical application of CNT-TFTs requires the production of large-area, highly uniform, density-controllable, repeatable, and high-throughput CNT thin films. In this study, CNT films were fabricated on 4-inch Si wafers and 2.5th generation (G2.5) backplane glasses (370 mm × 470 mm) by dip coating using a chloroform-dispersed high-purity semiconducting CNT solution. The CNT density was controlled by the solution concentration and coating times, but was almost independent of the substrate lifting speed (1–450 mm·min−1), which enables high-throughput CNT thin film production. We developed an image processing software to efficiently characterize the density and uniformity of the large-area CNT films. Using the software, we confirmed that the CNT films are highly uniform with coefficients of variance (CV) < 10% on 4-inch Si wafers and ∼ 13.8% on G2.5 backplane glasses. High-performance CNT-TFTs with a mobility of 45–55 cm2·V−1·s−1 were obtained using the fabricated CNT films with a high-performance uniformity (CV ≈ 11%–13%) on a 4-inch wafer. To our knowledge, this is the first fabrication and detailed characterization of such large-area, high-purity, semiconducting CNT films for TFT applications, which is a significant step toward manufacturing CNT-TFTs.

Highly flexible printed carbon nanotube thin film transistors using cross-linked poly(4-vinylphenol) as the gate dielectric and application for photosenstive light-emitting diode circuit

In this work, cross-linked poly(4-vinylphenol) (PVP) was utilized in printed single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) as the gate dielectric layer to achieve low operating voltage, environmental stability and high flexibility. The printed top-gate TFTs on polyethylene terephthalate (PET) substrates exhibited effective mobility up to 8.4 cm2V−1s−1 (based on device capacitances measured at 0.1 Hz), on/off ratio of 106 and subthreshold swing (ss) of 63.8 mV/dec at operation voltage of only 1 V. The printed TFTs exhibited excellent mechanical flexibility and stability under ambient conditions due to the use of cross-linked PVP as dielectric layers. No obvious discrepancies in electrical properties were observed after bending 15000 cycles at the radius of 5 mm. A photosensitive light-emitting diode (LED) circuit was constructed, which was composed of two commercial LEDs and the printed SWCNT TFTs. One LED was mounted on top of the gate electrode, acting as a photon sensor to modulate the gate voltage of TFT. The second LED was connected to the source electrode to act as an illuminating device. The circuit could drive the illuminating LED at Vdd of −0.75 V and Vds = −2 V with lighting intensity varying from 0 to 8.96 μW/cm2.

A new stage for flexible nanotube devices

Flexible integrated circuits built using carbon nanotube thin-film transistors can offer sub-10 ns stage delays.

Flexible CMOS integrated circuits based on carbon nanotubes with sub-10 ns stage delays

High-performance logic circuits that are constructed on flexible or unconventional substrates are required for emerging applications such as real-time analytics. Carbon nanotube thin-film transistors (TFTs) are attractive for these applications because of their high mobility and low cost. However, flexible nanotube TFTs usually suffer from much lower performance than those built on rigid substrates, and the resulting flexible integrated circuits typically exhibit low-speed operation with logic gate delays of over 1 μs, which severely limits their practical application. Here we show that high-performance carbon nanotube TFTs and complementary circuits can be fabricated on flexible polyimide substrates using a high-yield, scalable process. Our flexible TFTs exhibit state-of-the-art performance with very high current densities (>17 μA μm−1), large current on/off ratios (>106), small subthreshold slopes (<200 mV dec−1), high field-effect mobilities (~50 cm2 V−1 s−1) and excellent flexibility. We also develop a reliable n-type doping process, which allows us to fabricate complementary logic gates and integrated circuits on flexible substrates. With our approach, we build flexible ring oscillators that have a stage delay of only 5.7 ns. High-performance carbon nanotube thin-film transistors and complementary circuits can be fabricated on flexible substrates, including ring oscillators that have a stage delay of only 5.7 ns.

Large-Area High-Performance Flexible Pressure Sensor with Carbon Nanotube Active Matrix for Electronic Skin.

Artificial "electronic skin" is of great interest for mimicking the functionality of human skin, such as tactile pressure sensing. Several important performance metrics include mechanical flexibility, operation voltage, sensitivity, and accuracy, as well as response speed. In this Letter, we demonstrate a large-area high-performance flexible pressure sensor built on an active matrix of 16 × 16 carbon nanotube thin-film transistors (CNT TFTs). Made from highly purified solution tubes, the active matrix exhibits superior flexible TFT performance with high mobility and large current density, along with a high device yield of nearly 99% over 4 inch sample area. The fully integrated flexible pressure sensor operates within a small voltage range of 3 V and shows superb performance featuring high spatial resolution of 4 mm, faster response than human skin (<30 ms), and excellent accuracy in sensing complex objects on both flat and curved surfaces. This work may pave the road for future integration of high-performance electronic skin in smart robotics and prosthetic solutions.

Performance enhancement of carbon nanotube thin film transistor by yttrium oxide capping.

Carbon nanotube thin film transistors (CNT-TFTs) are regarded as promising technology for active matrix pixel driving circuits of future flat panel displays (FPD). For FPD application, unipolar thin film transistors (TFTs) with high mobility (μ), high on-state current (ION), low off-current (IOFF) at high source/drain bias and small hysteresis are required simultaneously. Though excellent values of those performance metrics have been realized individually in different reports, the overall performance of previously reported CNT-TFTs has not met the above requirements. In this paper, we found that yttrium oxide (Y2O3) capping is helpful in improving both ION and μ of CNT-TFTs. Combining Y2O3 capping and Al2O3 passivation, unipolar CNT-TFTs with high ION/IOFF (>107) and low IOFF (∼pA) at -10.1 V source/drain bias, and relatively small hysteresis in the range of -30 V to +30 V gate voltage were achieved, which are capable of active matrix display driving.

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec-1 and ON/OFF ratio of 106, which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 105) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Solution-processed single-wall carbon nanotube transistor arrays for wearable display backplanes

In this paper, we demonstrate solution-processed single-wall carbon nanotube thin-film transistor (SWCNT-TFT) arrays with polymeric gate dielectrics on the polymeric substrates for wearable display backplanes, which can be directly attached to the human body. The optimized SWCNT-TFTs without any buffer layer on flexible substrates exhibit a linear field-effect mobility of 1.5cm2/V-s and a threshold voltage of around 0V. The statistical plot of the key device metrics extracted from 35 SWCNT-TFTs which were fabricated in different batches at different times conclusively support that we successfully demonstrated high-performance solution-processed SWCNT-TFT arrays which demand excellent uniformity in the device performance. We also investigate the operational stability of wearable SWCNT-TFT arrays against an applied strain of up to 40%, which is the essential for a harsh degree of strain on human body. We believe that the demonstration of flexible SWCNT-TFT arrays which were fabricated by all solution-process except the deposition of metal electrodes at process temperature below 130oC can open up new routes for wearable display backplanes.

Designing hybrid gate dielectric for fully printing high-performance carbon nanotube thin film transistors

The electrical characteristics of carbon nanotube (CNT) thin-film transistors (TFTs) strongly depend on the properties of the gate dielectric that is in direct contact with the semiconducting CNT channel materials. Here, we systematically investigated the dielectric effects on the electrical characteristics of fully printed semiconducting CNT-TFTs by introducing the organic dielectrics of poly(methyl methacrylate) (PMMA) and octadecyltrichlorosilane (OTS) to modify SiO2 dielectric. The results showed that the organic-modified SiO2 dielectric formed a favorable interface for the efficient charge transport in s-SWCNT-TFTs. Compared to single-layer SiO2 dielectric, the use of organic–inorganic hybrid bilayer dielectrics dramatically improved the performances of SWCNT-TFTs such as mobility, threshold voltage, hysteresis and on/off ratio due to the suppress of charge scattering, gate leakage current and charge trapping. The transport mechanism is related that the dielectric with few charge trapping provided efficient percolation pathways for charge carriers, while reduced the charge scattering. High density of charge traps which could directly act as physical transport barriers and significantly restrict the charge carrier transport and, thus, result in decreased mobile carriers and low device performance. Moreover, the gate leakage phenomenon is caused by conduction through charge traps. So, as a component of TFTs, the gate dielectric is of crucial importance to the manufacture of high quality TFTs from the aspects of affecting the gate leakage current and device operation voltage, as well as the charge carrier transport. Interestingly, the OTS-modified SiO2 allows to directly print horizontally aligned CNT film, and the corresponding devices exhibited a higher mobility than that of the devices with the hybrid PMMA/SiO2 dielectric although the thickness of OTS layer is only ∼2.5 nm. Our present result may provide key guidance for the further development of printed nanomaterial electronics.

Realization of solution-processed semiconducting single-walled carbon nanotubes thin film transistors with atomic layer deposited ZrAlOx gate insulator

In this study, the semiconducting single-walled carbon nanotube (semi-SWCNT) thin film transistors (TFTs) with high dielectric constant (κ) atomic layer deposited ZrAlOx gate insulator are fabricated by the drop-casted method. The hysteresis characteristic, negative gate voltage stress stability, and thermal stability are studied, and the semi-SWCNT TFTs with ZrAlOx gate insulators show a small hysteresis of 0.2 V, a little threshold voltage shift of 2.5 V under the negative gate voltage stress, and a threshold voltage shift of 2 V under the thermal stress. Such advantages are due to the amorphous structure and smooth surface of the atomic layer deposited ZrAlOx gate insulator, which induces less trap states. In addition, the thermal stress stability of semi-SWCNT TFTs is investigated. It is found that the behavior of semi-SWCNT TFTs under thermal stress obeys the thermally activated hopping model obviously. This model explains the threshold voltage shift of the device under thermal stress, which is very reasonable.