Carbon Nanotube Field-effect Transistors Research Articles

Jiezi: An open-source Python software for simulating quantum transport based on non-equilibrium Green's function formalism

We present a Python-based open-source library named Jiezi, which provides the means of simulating the electronic transport properties of nanoscaled devices on the atomistic level. The key feature of Jiezi lies in its core algorithm, i.e., self-consistent orchestration between the non-equilibrium Green's function (NEGF) method and a Poisson's equation solver. Beyond the construction of the tight-binding (TB) Hamiltonian with empirical parameters for conventional materials, the package offers a comprehensive framework for constructing the Wannier-based Hamiltonian matrix, enabling the investigation of novel materials and their heterostructures. To expedite the solution of NEGF systems, a methodology based on renormalization theory is proposed for reducing the dimension of the Hamiltonian matrix. Additionally, we adopt a non-linear Poisson equation solver with no analytical approximation in this software. The software facilitates seamless integration with external tools for geometry and mesh generation and post-processing. In this paper, we present the main capabilities and workflow by demonstrating with a simulation for the carbon nanotube field-effect transistor (CNTFET). Program summaryProgram Title: JieziCPC Library link to program files:https://doi.org/10.17632/nk79kbtww4.1Developer's repository link:https://github.com/Jiezi-negf/JieziLicensing provisions: GPLv3Programming language: PythonNature of problem: Simulates the quantum transport property of nano-scaled transistors based on the predefined device structure and the material composition.Solution method: Solves the coupled Schrödinger equation and Poisson equation by NEGF and finite element method.

Numerical investigation on the convergence of self-consistent Schrödinger-Poisson equations in semiconductor device transport simulation

Semiconductor devices at the nanoscale with low-dimensional materials as channels exhibit quantum transport characteristics, thereby their electrical simulation relies on the self-consistent solution of the Schrödinger-Poisson equations. While the non-equilibrium Green’s function (NEGF) method is widely used for solving this quantum many-body problem, its high computational cost and convergence challenges with the Poisson equation significantly limit its applicability. In this study, we investigate the stability of the NEGF method coupled with various forms of the Poisson equation, encompassing linear, analytical nonlinear, and numerical nonlinear forms Our focus lies on simulating carbon nanotube field-effect transistors (CNTFETs) under two distinct doping scenarios: electrostatic doping and ion implantation doping. The numerical experiments reveal that nonlinear formulas outperform linear counterpart. The numerical one demonstrates superior stability, particularly evident under high bias and ion implantation doping conditions. Additionally, we investigate different approaches for presolving potential, leveraging solutions from the Laplace equation and a piecewise guessing method tailored to each doping mode. These methods effectively reduce the number of iterations required for convergence.

A portable transistor immunosensor for fast identification of porcine epidemic diarrhea virus

Widespread distribution of porcine epidemic diarrhea virus (PEDV) has led to catastrophic losses to the global pig farming industry. As a result, there is an urgent need for rapid, sensitive and accurate tests for PEDV to enable timely and effective interventions. In the present study, we develop and validate a floating gate carbon nanotubes field-effect transistor (FG CNT-FET)-based portable immunosensor for rapid identification of PEDV in a sensitive and accurate manner. To improve the affinity, a unique PEDV spike protein-specific monoclonal antibody is prepared by purification, and subsequently modified on FG CNT-FET sensor to recognize PEDV. The developed FET biosensor enables highly sensitive detection (LoD: 8.1 fg/mL and 100.14 TCID50/mL for recombinant spike proteins and PEDV, respectively), as well as satisfactory specificity. Notably, an integrated portable platform consisting of a pluggable FG CNT-FET chip and a portable device can discriminate PEDV positive from negative samples and even identify PEDV and porcine deltacoronavirus within 1 min with 100% accuracy. The portable sensing platform offers the capability to quickly, sensitively and accurately identify PEDV, which further points to a possibility of point of care (POC) applications of large-scale surveillance in pig breeding facilities.

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to the best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

SiX2 (X = S, Se) Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications.

The gate-all-around (GAA) field-effect transistor (FET) holds great potential to support next-generation integrated circuits. Nanowires such as carbon nanotubes (CNTs) are one important category of channel materials in GAA FETs. Based on first-principles investigations, we propose that SiX2 (X = S, Se) nanowires are promising channel materials that can significantly elevate the performance of GAA FETs. The sub-5 nm SiX2 (X = S, Se) nanowire GAA FETs exhibit excellent ballistic transport properties that meet the requirements of the 2013 International Technology Roadmap for Semiconductors (ITRS). Compared to CNTs, they are also advantageous or at least comparable in terms of gate controllability, device dimensions, etc. Importantly, SiSe2 GAA FETs show superb gate controllability due to the ultralow minimum subthreshold swing (SSmin) that breaks "Boltzmann's tyranny". Moreover, the energy-delay product (EDP) of SiX2 GAA FETs is significantly lower than that of the CNT FETs. These features make SiX2 nanowires ideal channel material in the sub-5 nm GAA FET devices.

Carbon Nanotube Field Effect Transistor Technology for Power Reduction

Carbon Nanotube Field Effect Transistor Technology for Power Reduction

Solution-processable low-voltage carbon nanotube field-effect transistors with high-k relaxor ferroelectric polymer gate insulator

Achieving energy-efficient and high-performance field-effect transistors (FETs) is one of the most important goals for future electronic devices. This paper reports semiconducting single-walled carbon nanotube FETs (s-SWNT-FETs) with an optimized high-k relaxor ferroelectric insulator P(VDF-TrFE-CFE) thickness for low-voltage operation. The s-SWNT-FETs with an optimized thickness (∼800 nm) of the high-k insulator exhibited the highest average mobility of 14.4 cm2 V−1s−1 at the drain voltage (I D) of 1 V, with a high current on/off ratio (I on/off >105). The optimized device performance resulted from the suppressed gate leakage current (I G) and a sufficiently large capacitance (>50 nF cm−2) of the insulating layer. Despite the extremely high capacitance (>100 nF cm−2) of the insulating layer, an insufficient thickness (<450 nm) induces a high I G, leading to reduced I D and mobility of s-SWNT-FETs. Conversely, an overly thick insulator (>1200 nm) cannot introduce sufficient capacitance, resulting in limited device performance. The large capacitance and sufficient breakdown voltage of the insulating layer with an appropriate thickness significantly improved p-type performance. However, a reduced n-type performance was observed owing to the increased electron trap density caused by fluorine proportional to the insulator thickness. Hence, precise control of the insulator thickness is crucial for achieving low-voltage operation with enhanced s-SWNT-FET performance.

Real-time, ultra-sensitive and label-free detection of OTA based on DNA aptamer functionalized carbon nanotube field-effect transistor

Ochratoxin A (OTA), widely recognized as a mycotoxin contaminant across various food products, poses significant health risks attributed to its nephrohepatotoxic and carcinogenic effects. Consequently, detecting OTA is crucial for ensuring food safety and preventing mycotoxicosis. In our study, we employed a carbon nanotube field-effect transistor (CNT FET) functionalized with DNA aptamers for targeted OTA detection. The sensor achieved a remarkably low detection threshold of 0.2 femtomolars (fM) in phosphate-buffered saline (PBS), enabling real-time detection of OTA over a broad concentration spectrum spanning from 8 fM to 80 pM. This research confirmed the sensor’s superior selectivity by effectively distinguishing OTA from non-target fungal toxins and showcased its rapid analysis capabilities across diverse complex matrices. Utilizing homogenized liquids from ten representative food samples for analysis, the sensor delivered real-time responses within 100 s, accurately identifying varying OTA concentrations down to 80 fM. In conclusion, this biosensor provides a label-free, highly sensitive, and rapid detection method for OTA, introducing novel solutions for effective mycotoxin surveillance in food safety. This biosensor also paves the way for the creation of a multiplex platform for concurrent monitoring of multiple fungal toxins.

A Host Receptor Nanodisc-Based Biosensor Platform for the Detection of a Specific Virus and Its Variants.

The host receptor is a key element in the initial stage of the virus entry into the host. The use of this host receptor is valuable as a sensing element for selectively and sensitively detecting specific viruses. Also, viruses tend to escape neutralizing antibodies through viral mutation but still utilize the cell entry process using the same host receptors, so it would be a powerful detection tool even for the mutant viruses. The angiotensin-converting enzyme 2 (ACE2) receptor, which is the representative host receptor, performs an essential function in facilitating viral penetration by interacting with the receptor-binding domain (RBD) of the SARS-CoV-2 spike protein. In this study, we introduce a novel approach, where we fabricated a carbon nanotube field-effect transistor (CNT-FET) sensor and combined it with ACE2 receptor-embedded nanodisc (ND). ACE2 was produced using an E. coli expression system, purified, and integrated into the ND platform. ACE2 NDs showed robust functionality through interactions with a pseudotyped virus (PV) containing the spike protein, enabling sensitive detection of both SARS-CoV-2 and its genetic variations at 102 PFU/mL. The ACE ND-based sensor exhibited excellent selectivity by accurately differentiating SARS-CoV-2 wild-type and variants (Omicron, Delta) from other viruses (ZIKA and MERS-CoV). As a result of comparative analysis, ACE2 ND showed approximately 49% superior long-term functionality up to the second week compared to that of soluble ACE2. These findings highlight the high selectivity and sensitivity of host receptor-based sensors for detecting viral variants and provide a promising tool to prevent the spread of unknown viruses.

A reliable non‐volatile in‐memory computing associative memory based on spintronic neurons and synapses

AbstractThis article introduces an innovative non‐volatile associative memory (AM) that leverages spintronic synapses, employing magnetic tunnel junctions (MTJ) in conjunction with neurons constructed using carbon nanotube field‐effect transistors (CNTFETs). Our proposed design represents a significant advancement in area optimization and outperforms prior designs. We adopt MTJ‐based spintronic devices due to their remarkable attributes, including dependable reconfigurability and nonvolatility. Simultaneously, CNTFETs effectively address the longstanding limitations traditionally associated with MOSFETs. In this work, our proposed design undergoes rigorous simulations that account for process variations. The results demonstrate that our AM system closely approximates its ideal mathematical model, even with significant process variations. Furthermore, we investigate the impact of Tunnel Magnetoresistance (TMR) on the performance of our proposed AM system. Our investigations reveal that, even with a TMR as low as 100%, our design matches and often surpasses the performance of its counterparts operating with a TMR of 300%. This achievement holds profound significance from a fabrication standpoint, as fabricating MTJs with high TMR values can be intricate and costly. Overall, our novel AM system represents a significant breakthrough in emerging technologies, harnessing the unique strengths of spintronic synapses and advanced carbon nanotube transistors while robustly addressing challenges in performance and variability.

Ultra-sensitive and rapid detection of Salmonella enterica and Staphylococcus aureus to single-cell level by aptamer-functionalized carbon nanotube field-effect transistor biosensors

Foodborne diseases caused by Salmonella enterica (S. enterica) and Staphylococcus aureus (S. aureus) significantly impact public health, underscoring the imperative for highly sensitive, rapid, and accurate detection technologies to ensure food safety and prevent human diseases. Nanomaterials hold great promise in the development of high-sensitivity transistor biosensors. In this work, field-effect transistor (FET) comprising high-purity carbon nanotubes (CNTs) were fabricated and modified with corresponding nucleic acid aptamers for the high-affinity and selective capture of S. enterica and S. aureus. The aptamer-functionalized CNT-FET biosensor demonstrated ultra-sensitive and rapid detection of these foodborne pathogens. Experimental results indicated that the biosensor could detect S. enterica at a limit of detection (LOD) as low as 1 CFU in PBS buffer, and S. aureus at an LOD of 1.2 CFUs, achieving single-cell level detection accuracy with exceptional specificity. The biosensor exhibited a rapid response time, completing single detections within 200 s. Even in the presence of interference from six complex food matrices, the biosensor maintained its ultra-sensitive (3.1 CFUs) and rapid response (within 200 s) characteristics for both pathogens. The developed aptamer-functionalized CNT-FET biosensor demonstrates a capability for low-cost, ultra-sensitive, label-free, and rapid detection of low-abundance S. enterica and S. aureus in both buffer solutions and complex environments. This innovation holds significant potential for applying this detection technology to on-site rapid testing scenarios, offering a promising solution to the pressing need for efficient and reliable pathogen monitoring in various settings.

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.

Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts.

CNT thin films based on epoxy mixtures: fabrication, electrical characteristics

The simple scaling of silicon transistors no longer ensures the advantages of high energy efficiency, driving research into nanotechnologies beyond silicon. Specifically, digital circuits based on carbon nanotube (CNT) field-effect transistors promise significant advantages in energy efficiency. However, the inability to perfectly control internal nanoscale defects and the variability of carbon nanotubes hinder the realization of very large-scale integrated systems. In this study, we investigated a novel method for fabricating transistors based on carbon nanotubes (CNTs) using epoxy mixtures, obtained the electrical properties of the transistors, and compared their microstructure and composition via the scanning electron microscopy. The carrier mobility on epoxy-based transistors was 28.87 cm²/V∙s, and the transistor switching frequency was 2.2 MHz. The samples exhibited electrical and physical stability over an extended period of time. The use of carbon nanotubes in epoxy resin as a conducting layer for transistors opens significant prospects in the field of electronics. The CNT-epoxy mixture technology allows for more flexible and rapid fabrication of thin-film transistors compared to classical methods. However, it is not appropriate to speak of a complete replacement; in this study, we present an alternative method for producing thin-film transistors, which may be of interest for specific purposes.

Design of new low-power and high-speed quaternary flip-flops based on CNTFETs

In this paper, novel configurations of a quaternary edge-sensitive flip-flop are introduced. They are realized by employing carbon nanotube field-effect transistors (CNTFETs). The first structure is based on a tri-state quaternary buffer integrated into a multiplexer. In the second proposed design, a quaternary input is decoded and then stored by tri-state binary buffers. In the end, binary values are converted to a quaternary value again. Finally, the last proposed circuit is not a d-type flip-flop; instead, a quaternary value is loaded by two controlling signals. The innovative configurations reduce the number of transistors, power consumption, and delay compared to previous approaches. The proposed designs are simulated and tested using HSPICE software and the CNTFET 32 nm library. The simulation results exhibit promising performance for the given quaternary flip-flops. For example, while having eight fewer transistors, the first proposed design has 87.7% higher performance in terms of power-delay product compared to one of the competitors with a similar structure. Finally, a quaternary shift register and a quaternary counter are also implemented to demonstrate the applicability of the third proposed quaternary FF in larger sequential circuits.

A Compact Model of Carbon Nanotube Field-Effect Transistors for Various Sizes with Bipolar Characteristics

Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths (Lref), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model’s validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V.

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Multiple Value Logic (MVL) circuits in high-speed digital systems can represent significantly more information than traditional binary logic circuits. The increasing demand for enhanced data storage capacity has driven the adoption of MVL circuits. However, designing MVL circuits presents challenges, particularly in achieving improved performance aligned with the desired threshold voltage. To address this challenge, harnessing carbon nanotube field-effect transistors (CNTFETs) has been instrumental in designing MVL circuits. CNTFETs offer distinct advantages due to their large resistors. Furthermore, substituting these resistors with Resistive Random Access Memory (RRAM) to implement Ternary logic circuits enhances storage capacity by enabling multiple resistance states within a single cell. This paper presents a novel MVL circuit design that leverages the unique characteristics of CNTFETs and RRAM. Additionally, gate implementation is explored using a Recurrent Neural Network − Long-Short Term Memory (RNN-LSTM) based Tasmanian Devil Optimization algorithm. The practical implementation uses Synopsis HSPICE software with CNTFET technology at 32 nm. A comprehensive performance analysis compares this approach with state-of-the-art solutions regarding delay, area, and power consumption. Significant reductions in area, power consumption, and transistor count are revealed with the proposed approach.

A Compact Model for Carbon Nanotube Field Effect Transistors Incorporating Temperature Effects and Application for Operational Amplifier Design

Semiconducting carbon nanotubes (CNTs), characterized by high carrier mobility and atomic thickness, are considered ideal channel materials for building high-performance and ultimate-scale field-effect transistors for future electronics. Here, we present a data-calibrated compact model of CNT field-effect transistors (CNTFETs) that incorporates temperature effects using the virtual source approach. The proposed model also includes the self-heating effect. Temperature effect was characterized by the influence of temperature on devices, achieved through establishing a temperature-dependent semi-empirical model of carrier mobility and carrier velocity. The proposed model can be easily implemented in a simulator. We designed a two-stage operational amplifier (OPAMP) using the proposed model at 32 nm technology. Compared with other studies, the designed CNTFET-based OPAMP demonstrates lower power consumption, which is beneficial for exploring the biological applications of low-power analog circuits in portable electronic devices. Furthermore, the impact of thermal variations on the design of OPAMP, as per the proposed model, was delineated. Investigations revealed that our circuit maintains a high common mode rejection ratio, which diminishes as the temperature increases and exhibits a moderate gain value that escalates with temperature.

DAFA: Dynamic approximate full adders for high area and energy efficiency

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard.

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.