Carbide Junction Field Effect Transistor Research Articles

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extremeenvironment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Influence of Gate Depletion Layer Width on Radiation Resistance of Silicon Carbide Junction Field-Effect Transistors

Silicon carbide junction field-effect transistors (SiC JFETs) are promising candidates as devices applicable to radiation conditions, such as the decommissioning of nuclear facilities or the space environment. We investigate the origin of the threshold volage (Vth) shift and hysteresis of differently structured SiC JFETs. A large positive Vth shift and hysteresis are observed for a depletion-type JFET with a larger depletion layer width. With changing the sweep range of the gate voltage and depletion width, the Vth shift was positively proportional to the difference between the channel depth and depletion width (channel depth–gate depletion width). By illuminating the sub-band gap light, the Vth of the irradiated depletion JFETs recovers close to nonirradiated ones, while a smaller shift and hysteresis are observed for the enhancement type with a narrower width. It can be interpreted that positive charges generated in a gate depletion layer cause a positive Vth shift. When they are swept out from the depletion layer and trapped in the channel, this gives rise to a further Vth shift and hysteresis in gamma-irradiated SiC JFETs.

Cascaded SiC JFET Topology for High-Voltage Solid-State Circuit Breaker Applications

With evolving landscape of direct current (DC) power transmission and distribution, a reliable and fast protection against faults is critical. High performance DC solid-state circuit breakers (SSCBs) can be designed using silicon carbide (SiC) junction field-effect transistors (JFETs), which utilize the device's intrinsic normally-ON characteristic and low ON-resistance. However, for SSCB that require high-voltage (HV) blocking capability, a proper number of JFETs need to be connected in series to achieve the desired voltage blocking rating. It has been conventional to add a controlling normally-OFF transistor, such a metal-oxide-semiconductor field-effect transistor (MOSFET), resulting in a circuit with normally-OFF behavior. However, disparities both in the voltage rating and in the ON-resistance between MOSFETs and JFETs tend to complicate the circuit design, and physically, they may lead to serious localized thermal stresses. A significant challenge remains with ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage as it is crucial to prevent permanent damages from over-voltage stresses. Therefore, this article presents a new switch topology, in which a cascaded JFET configuration is operated without using a control MOSFET or other added control device. The dynamic voltage balancing network to synchronize both the JFETs' turn ON and OFF intervals is described analytically. Moreover, a novel static voltage balancing network is proposed to establish equal sharing of the total blocking voltage across the series connection of JFETs while maintaining low power loss.

A 60-MHz Silicon Carbide Voltage-Controlled Oscillator for Extreme Temperature Applications

In this brief, a custom-built silicon carbide (SiC) junction field-effect transistor (JFET) is characterized from room temperature to 52°C, and a 60 MHz voltage-controlled oscillator (VCO) based on this SiC JFET is designed and fabricated through low temperature co-fired ceramic (LTCC) process. The test results of the VCO prototype demonstrate that the proposed SiC JFET VCO is capable of operating from 25 °C to 500 °C. RF signal of 50dB above the noise floor is generated, and the tuning gain of 9.22 kHz/V is achieved at 500 °C. The proposed SiC JFET VCO can serve as the fundamental building block for wireless sensing or data communication in extreme temperature industrial and space applications.

Latching Current Limiter for Space Platform Power Distribution Using a Low-Voltage p-MOSFET and a Normally-ON SiC JFET

Power distribution using latching current limiters (LCLs) [also known as solid-state power controllers (SSPCs)] is very common for 28- and 50-V bus voltage distribution on European satellite platforms. However, 100-V and even higher voltage distribution platforms generally do not employ the same approach as lower bus voltage platforms since the commonly employed p-MOSFET devices are not well suited for such voltage levels. This work introduces an LCL for 100-V distribution units using a composite power device consisting of a low-voltage p-MOSFET device and a high-voltage, normally-ON silicon carbide junction field effect transistor (SiC JFET). The description of the circuit and the experimental validation using a hypothetical class-2 (2.2–2.8 A), 100-V, LCL is discussed. In addition, in this work, two interesting characteristics are also proposed and validated, and automatic control of the tripping time depending on the overload severity and soft starts for capacitive inrush currents. Robustness and fast reaction, less than 500 ns under short-circuit conditions, have been demonstrated, as well as tight current regulation during overload faults.

Power Loss Reduction Control for Modular Multilevel Converters Based on Resistor Controllable Submodule

A bleeding resistor is usually adopted to be parallel with the capacitor in the submodule (SM) to avoid static voltage imbalance caused by auxiliary power supply during start-up process of modular multilevel converters (MMCs). However, the bleeding resistor causes unnecessary power loss during normal operation. In this article, a resistor controllable SM based on a normally- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> silicon carbide (SiC) junction field-effect transistor is proposed to reduce the power loss on bleeding resistor at normal operation of MMCs. The proposed control can not only ensure the static voltage balance during start-up of MMCs, but can also completely eliminate the power loss on bleeding resistor during normal operation of MMCs for high efficiency. In addition, the proposed control can shorten the SM capacitor discharging time at shut-down process. Experimental studies are conducted and the results confirm the effectiveness of the proposed control.

Short-Circuit Failure Mechanisms of 650-V GaN/SiC Cascode Devices in Comparison With SiC MOSFETs

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad.

A High-Performance 4H-SiC JFET With Reverse Recovery Capability and Low Switching Loss

A novel high-performance 1700-V 4H-Silicon carbide (SiC) junction field-effect transistor (JFET) with reverse recovery capability and low switching loss is proposed in this article. As for the proposed 4H-SiC JFET, the gate region of the conventional 4H-SiC JFET is split into two segments, one of which is replaced by the source. A Schottky barrier diode (SBD) is integrated in the sidewall of the channel region, which greatly improves the performances of the 4H-SiC JFET. Compared with the conventional 4H-SiC JFET, the numerical simulation results show that the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON},\text{ sp}}$ </tex-math></inline-formula> ), gate–drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text{GD}}$ </tex-math></inline-formula> ), and gate–drain charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{\text{gd}}$ </tex-math></inline-formula> ) of the proposed 4H-SiC JFET are reduced by 25.57%, 99.96%, and 72.91%, respectively. The switching loss is reduced by about 91%, and the average gate drive power consumption is reduced by more than 36% while the frequency range is from 10 to 400 kHz. The results also demonstrate that the proposed device has good reverse recovery performance and reduces switching loss, compared with the current commercial SiC devices.

Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

Abstract At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 μm to 2 μm) coupled with enlarged die size (from 3 × 3 mm to 5 × 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

Experimental Study on Short-Channel Effects in Double-Gate Silicon Carbide JFETs

Short-channel effects (SCEs) in double-gate silicon carbide junction field-effect transistors (JFETs) fully fabricated by ion implantation are experimentally investigated. The threshold voltage shift, drain-induced barrier lowering, and subthreshold slope degradation are clearly observed in the fabricated p- and n-JFETs. The SCEs are quantitatively evaluated by comparing with the theoretical values obtained by solving a 2-D Poisson equation, which shows good agreement with experiments. The dominant parameter for the SCEs in JFETs is the ratio of the channel length ( ${L}$ ) to the channel thickness ( ${a}$ ), and the device scaling rule to avoid the SCEs is estimated to be ${L}/{a} > {3}$ .

Radiation Hardness of 4H-SiC JFETs in MGy Dose Ranges

Silicon carbide junction field effect transistors (SiC JFETs) were irradiated with gamma-rays up to 9 MGy (H2O). With increasing dose, apparent shift of drain current-gate voltage (ID-VG) curves to negative voltage side as observed for SiC metal oxide semiconductor (MOS) FETs did not take place. No significant difference is observed between drain and gate leakage currents of irradiated JFETs. This strongly indicates that defects as leakage paths were introduced into not bulk region but the interface between bulk and the passivation layer of SiO2. While, the transfer characteristics including threshold voltage and transconductance were slightly changed compared with the pristine sample. After drain voltage (VD) was abruptly applied to 6 V, ID at VG= 0 V increased slowly as a function of time. This indicates that variation of transfer characteristics is attributed to capture and emission process at defects generated in channel region.

Short Circuit Fault Discrimination Using SiC JFET Based Self-Powered Solid State Circuit Breakers in a Residential DC Community Microgrid

This article identifies and validates the use of ultrafast silicon carbide (SiC) junction field effect transistor (JFET)-based self-powered solid-state circuit breakers (SSCBs) as the enabling protective device for a 340 Vdc residential dc community microgrid. These SSCBs will be incorporated into a radial distribution system in order to enhance fault discrimination through autonomous operation. Because of the nature and characteristics of short-circuit fault inception in dc microgrids, the time–current trip characteristics of protective devices must be several orders of magnitude faster than conventional circuit breakers. The proposed SSCBs detect short-circuit faults by sensing the sudden voltage rise between its two power terminals and draw power from the fault condition itself to turn off SiC JFETs and then, coordinate with no-load contacts that can isolate the fault. Depending upon the location of the SSCBs in the microgrid, either unidirectional or bidirectional implementations are incorporated. Cascaded SSCBs are tuned using a simple resistor change to enable fault discrimination between upstream high-current feeds and downstream lower current branches. Operation of one of the SSCBs and three in cascaded arrangements are validated both in simulation and with a hardware test platform. Thermal impact on the SSCB is discussed as well. The target application is a residential dc microgrid that will be installed as part of a revitalization effort of an inner city Milwaukee neighborhood.

Characterization of Static and Dynamic Behavior of 1200 V Normally off GaN/SiC Cascode Devices

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p -GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on -resistance ( R ON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage ( V TH), and no dynamic R ON degradation. To identify its safe operation in the off -state with a high drain bias, the off -state middle point voltage ( V M) between the E-mode device drain and D-mode device source is investigated. A relatively low off -state V M is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic V TH shift; and 2) suppress the increased dynamic off -state leakage current ( I OFF) induced by on -state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn- on and 121 V/ns during turn- off is achieved.

Analysis and Modeling of SiC JFET Bi-Directional Switches Parasitic Oscillation

Silicon carbide (SiC) junction field-effect transistor (JFET) based bi-directional switches (BDSs) have great potential in the construction of several power electronic circuits, including matrix converters, multi-level converters, solid state breakers, and so on. Parasitic oscillation in SiC JFET-based BDSs has direct impact on the stability and reliability of these circuits. Proper handling of parasitic oscillation becomes highly critical. This paper focuses on the parasitic oscillation suppression in SiC JFET-based BDSs. A parallel snubber capacitor or a series ferrite ring was often used to damp parasitic oscillation in switching circuits in the literature. However, conventionally, the snubber capacitance was obtained by time-consuming and labour-intensive trial-and-error methods. The main contribution of this study is to derive the simplified equivalent transient circuit of the SiC JFET-based BDS considering all parasitic elements and quantitatively define the reasonable range of the snubber capacitance. And the combined effect of the selected snubber capacitance and the selected ferrite ring is investigated. In the end, simulation and experimental results validate the effectiveness of the proposed method.

Dynamic Voltage Balancing for the High-Voltage SiC Super-Cascode Power Switch

Presented in this paper is an optimization method to improve the dynamic performance of high-voltage super-cascode power switches (SCPSs) by implementing silicon carbide (SiC) junction field-effect transistor (JFET). The basic operating principle of SCPS is explained at the beginning of the paper. Equivalent circuit models are outlined next, with equations describing the voltage distribution among each SiC JFET during switching transients. Based on the sensitivity analysis, a component optimization method for balancing the SCPS internal voltage is proposed, which effectively eliminates the overvoltage. This significantly reduces the switching loss and the chance of diode avalanche. Compared with the nonoptimized case, the turn-on loss of the SCPS is reduced to 8.85%, and the turn-off loss reduces to 48.4%.

Forced Current Balancing of Parallel-Connected SiC JFETs During Forward and Reverse Conduction Mode

In this paper, a thorough investigation on the parallel connection of the latest generation vertical trench silicon carbide (SiC) junction field-effect transistors (JFETs) during forward and reverse conduction is performed. Both enhancement and depletion mode SiC JFETs are examined, regarding their static and dynamic characteristics. A parametric analysis on the current sharing, reliability, and effectiveness of the parallel connection is carried out. Current asymmetry over the different JFETs is monitored via series-connected current transformers. A forced current balancing technique during forward conduction mode is achieved by controlling the time delay of the gate signal through a low-cost digital signal controller. The drain current mismatch during reverse conduction is also studied and addressed by applying similar techniques as in the forward conduction, or by adding an antiparallel power diode. The performance of paralleled JFETs is validated through simulation and experimental results at room temperature and 150 °C.

Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions

The prolonged operation of semiconductor integrated circuits (ICs) needed for long-duration exploration of the surface of Venus has proven insurmountably challenging to date due to the ∼ 460 °C, ∼ 9.4 MPa caustic environment. Past and planned Venus landers have been limited to a few hours of surface operation, even when IC electronics needed for basic lander operation are protected with heavily cumbersome pressure vessels and cooling measures. Here we demonstrate vastly longer (weeks) electrical operation of two silicon carbide (4H-SiC) junction field effect transistor (JFET) ring oscillator ICs tested with chips directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus’ surface atmosphere. This represents more than 100-fold extension of demonstrated Venus environment electronics durability. With further technology maturation, such SiC IC electronics could drastically improve Venus lander designs and mission concepts, fundamentally enabling long-duration enhanced missions to the surface of Venus.

Applications, Prospects and Challenges of Silicon Carbide Junction Field Effect Transistor (SIC JFET)

Properties of Silicon Carbide Junction Field Effect Transistor (SiC JFET) such as high switching speed, low forward voltage drop and high temperature operation have attracted the interest of power electronic researchers and technologists, who for many years developed devices based on Silicon (Si). A number of power system Engineers have made efforts to develop more robust equipment including circuits or modules with higher power density. However, it was realized that several available power semiconductor devices were approaching theoretical limits offered by Si material with respect to capability to block high voltage, provide low on-state voltage drop and switch at high frequencies. This paper presents an overview of the current applications of SiC JFET in circuits such as inverters, rectifiers and amplifiers. Other areas of application reviewed include; usage of the SiC JFET in pulse signal circuits and boost converters. Efforts directed toward mitigating the observed increase in electromagnetic interference were also discussed. It also presented some areas for further research, such as having more applications of SiC JFET in harsh, high temperature environment. More work is needed with regards to SiC JFET drivers so as to ensure stable and reliable operation, and reduction in the prices of SiC JFETs through mass production by industries.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 °C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C).