Capacitor-less Low-dropout Voltage Regulator Research Articles

A Transient-Enhanced Capacitorless LDO Design

Abstract This paper introduces a capacitor-less low drop-out voltage regulator (LDO) designed for fast transient response. Traditional capacitor-less LDOs often suffer from suboptimal transient responses, leading to unstable outputs during load transitions. To address this challenge, the circuit employs voltage rise and fall suppression circuits to mitigate voltage spikes. It utilizes slew rate enhancement techniques to improve the transient response characteristics of the LDO. Miller compensation is applied to achieve phase margin compensation with a smaller capacitor area. Simulation outcomes indicate that within the voltage range of 2.2 V to 3.3 V, the circuit provides a stable output voltage of 1.8 V while accommodating a peak load current of 100 mA. When the load current undergoes a step change between 1 mA and 100 mA, the transient enhancement circuit reduces the undershoot of the output voltage by 58 mV, a decrease of 39%, with a response time of 1.13 μs. The overshoot amplitude is reduced by 212 mV, a decrease of 70.6%, with a response time of 1.21 μs.

Design of high reliability LDO regulator with NLRSCR based ESD protection circuit using dynamic feedback loop for low-voltage applications

Capacitor-less low dropout voltage regulator applied to the mobile devices consistently exposes the peak voltage, which can increase the power consumption. This study proposes a dynamic feedback loop of the LDO regulator that provides a function to stably control the peak voltage irrespective of the change of the load current. The performance of the chip layout was evaluated under conditions of an output voltage of 3 V, a battery input voltage of 3.3 to 4.5 V, and a load current of 350 mA. As a result, the peak voltage keeps an undershoot voltage of 30 mV and an overshoot of 33 mV along the load current. In addition, the demand for miniaturization and integration of ICs and the application of low voltage applications are increasing. Thereby, the circuit damage due to ESD (Electro Static Discharge) may happen frequently. This is a significant factor influencing the overall reliability related to productivity and stability. In this study, we confirmed that the proposed LDO regulator with the ESD protection circuit of the NLRSCR structure secures high reliability at low voltage.

Fast‐transient high‐performance 0.18 μm CMOS LDO for battery‐powered systems

A low-power 0.18 µm CMOS capacitor-less low-dropout voltage regulator for battery-operated portable devices is presented. A high-gain telescopic cascode-compensated amplifier is used to attain a stable topology with good static performances, while a very simple dynamic biasing circuit significantly enhances transient performances with no quiescent current penalty. Post-layout results show a 1.8 V output voltage from a 3.6 to 1.9 V battery input voltage, delivering a 50 mA load current over a 100 pF load. The quiescent current is only 7 µA, the line and load regulations are, respectively, 0.039 mV/V and 0.17 mV/mA, and settling times are lower than 3.9 µs at full load transient.

Hybrid Feedback Compensation of an External Capacitor-less Low Dropout Voltage Regulator

Power management has an ever increasing presence in the electronics industry due to the growth of battery powered mobile devices. The low-dropout voltage regulator (LDO) offers improved efficiency over other regulator topologies. However, the architecture suffers from stability issues, which usually necessitates a large off-chip capacitor to ensure the regulator’s performance. This paper presents an alternative topology by removing the bulky external capacitor, thus allowing for greater power system integration. The proposed Current Amplifier Hybrid Compensation (CAHC) scheme implements an active feedback-feedforward compensation system and maintains both a fast transient response and full range alternating current (AC) stability from 0 to 50mA load currents even with a 100pF loading capacitance. The 1.2V External Capacitor-less LDO voltage regulator was designed and simulated in a commercial 0.35um CMOS technology, consuming only 61uA of quiescent current with a dropout voltage of less than 200mV. Simulated results demonstrate that the proposed External Capacitor-less LDO architecture overcomes the typical load transient and AC stability issues encountered in previous architectures. The combined size and component reduction of this architecture presents a more integrable and economic power management system.

Full On-Chip CMOS Low-Dropout Voltage Regulator

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.